[U-Boot-Users] TQM866 SDRAM Table

SETTE AGOSTINO - technolabs Agostino.Sette at technolabs.it
Tue Mar 21 15:30:20 CET 2006

I am currently using a TQM866 with a cpu clock of 133MHz and I have
problems with the configuration of the SDRAM.
Here attached there is the sdram_table from the following file: 
#define _NOT_USED_      0xFFFFFFFF
const uint sdram_table[] =
         * Single Read. (Offset 0 in UPMA RAM)
        0x1F0DFC04, 0xEFAFBC04, 0x1EAF7C04, 0xF1AFFC04,
        0xEFBAFC00, 0x1FF5FC47, _NOT_USED_, _NOT_USED_, /* last */
         * Burst Read. (Offset 8 in UPMA RAM)
        0x1F0DFC04, 0xEFAFBC04, 0x1EAF7C04, 0xF0AFFC04,
        0xF0AFFC00, 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, /* last */
        0x1FF5FC47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
         * Single Write. (Offset 18 in UPMA RAM)
        0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0xFFFFFC04,
        0x1FF5FC47, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* last */
         * Burst Write. (Offset 20 in UPMA RAM)
        0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
        0xF0AFFC00, 0xE1BAFC04, 0xFFFFFC04, 0x1FF5FC47, /* last */
         * SDRAM Initialization (offset 2C in UPMA RAM)
         * This is no UPM entry point. The following definition uses
         * the remaining space to establish an initialization
         * sequence, which is executed by a RUN command.
        0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, _NOT_USED_, /* last */
         * Refresh  (Offset 30 in UPMA RAM)
        0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
        0xFFFFFC84, 0xFFFFFC07, _NOT_USED_, _NOT_USED_, /* last */
         * Exception. (Offset 3c in UPMA RAM)
        0xFFFFFC07, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* last */
We have only the following custom connections:
RAS --> GPL2
A10  --> GPL0
CAS --> GPL3
WE  --> GPL1
Freescale said that the SDRAM timing is determined by patterns
programmed by the user in the UPM (User Programmable Machine). 
According to the SDRAM manufacturers specification the "Write Recovery
Time" tWR is 15ns minimum. 
In the current UPM patterns  they  see only one clock period for tWR.
The clock period can be determined as follows: 
This also explains why the board works ok when the core frequency is
reduced to 130MHz, since this translates to a bus clock period of
They asked to insert another clock period in the UPM pattern for "Write
Recovery Time". 
I would like to know how to modify the table to introduce the
modification suggested by Freescale.  
Thanks in advance for you support
Agostino Sette
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