[U-Boot-Users] BRGs on ep8248 after updating CLKIN

[Erik Christiansen]

On Thu, Nov 29, 2007 at 01:43:30PM -0700, Alan Bennett wrote:
> When I originally supported my ep8248-style board, I had
> #define CONFIG_8260_CLKIN	66000000	/* in Hz */
> 
> However, I noticed (after far too much time had passed) that my cpu
> speed wasn't matching my expectations.  (reported 230 MHz, and
> expected 350 MHz).
> 
> This was rather easily fixed by changing the CONFIG_8260_CLKIN to 100 MHz:
> #define CONFIG_8260_CLKIN	100000000	/* in Hz */
> 
> However, my BRGs / SMC1 uart is now broke(baud-rate mismatch).  Does
> anyone have experience with this section of u-boot that could help me
> out?

Only that U-Boot built and ran fine for me on an ep8248 board, without
any need to change the default CONFIG_8260_CLKIN.

If the "ep8248-style board" were mine, I'd physically compare the
crystal frequency with a real ep8248, before adjusting
CONFIG_8260_CLKIN. (Assuming PLL config is unchanged.) 

What does a frequency meter or CRO show on core_clk_out, during
core_hreset, on yours? Incidentally, mine also reports:

CPU:   MPC8248 (HiP7 Rev 14, Mask 1.0 1K50M) at 231 MHz
Board: EP8248E 1.0 CPLD revision 2

> My BRG7 is configured by u-boot(1.3+) = 0x00010078 ~ CD = 60 (0x3c).
> And there is an apparent baud-rate mismatch and all the output is
> garbled now.  (with a scope I measured ~ 25.5 / 26 K, when I'm
> expecting 38.4k)
> 
> I think I'm missing something in the equation, but I'm not sure where
> it is.  If I simply update the CD to be 162 (162*38400*16 = 99,532,800
> ~ 100 MHz) the serial port is still dead.
> 
> Any ideas?

>From way over here, it looks a bit like an incorrect assumption. But
that's based on my tentative understanding that 350 MHz is "expected",
but 230 MHz works. (Serial was OK in that case.)

What is it that doesn't work with the default CONFIG_8260_CLKIN?
(And if it's only low CPU speed, then a higher crystal frequency or
lower PLL divider will be of more benefit?)

Regards,
Erik