[U-Boot] [PATCH 3/5] fsl-ddr: make the self refresh idle threshold configurable

[Andy Fleming]

On Fri, Nov 21, 2008 at 2:31 AM, Dave Liu <daveliu at freescale.com> wrote:
> Some 85xx processors have the advanced power management feature,
> such as wake up ARP, that needs enable the automatic self refresh.
>
> If the DDR controller pass the SR_IT (self refresh idle threshold)
> idle cycles, it will automatically enter self refresh. However,
> anytime one transaction is issued to the DDR controller, it will
> reset the counter and exit self refresh state.
>
> Signed-off-by: Dave Liu <daveliu at freescale.com>

Applied to 85xx-next, thanks