[U-Boot] [PATCH 2/3] 85xx: Fix the wrong CSIZE mask bit

[Dave Liu]

The CSIZE is L1CFG0[56-63] in the e500 and e500mc core,
so we should mask 0xff, not 0x1ff.

Signed-off-by: Dave Liu <daveliu at freescale.com>
---
 cpu/mpc85xx/start.S |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 80f9677..cfa53c0 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -244,7 +244,7 @@ switch_as:
 	lis	r3,CONFIG_SYS_INIT_RAM_ADDR at h
 	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR at l
 	mfspr	r2, L1CFG0
-	andi.	r2, r2, 0x1ff
+	andi.	r2, r2, 0xff
 	/* cache size * 1024 / (2 * L1 line size) */
 	slwi	r2, r2, (10 - 1 - L1_CACHE_SHIFT)
 	mtctr	r2
@@ -1004,7 +1004,7 @@ unlock_ram_in_cache:
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
 	ori	r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
 	mfspr	r4,L1CFG0
-	andi.	r4,r4,0x1ff
+	andi.	r4,r4,0xff
 	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
 	mtctr	r4
 1:	dcbi	r0,r3
-- 
1.5.4