[U-Boot] [RFC] nand boot for 85xx

Kumar Gala kumar.gala at freescale.com
Thu Dec 18 08:00:09 CET 2008


On Dec 18, 2008, at 12:20 AM, Dave Liu wrote:

> diff --git a/board/freescale/mpc8572ds/nand_boot.c b/board/freescale/ 
> mpc8572ds/nand_boot.c
> new file mode 100644
> index 0000000..1fb0acd
> --- /dev/null
> +++ b/board/freescale/mpc8572ds/nand_boot.c
> @@ -0,0 +1,75 @@
> +/*

> +
> +#include <common.h>
> +#include <ns16550.h>
> +#include <nand.h>
> +#include <asm/mmu.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/fsl_law.h>
> +#include <asm/io.h>
> +
> +unsigned long get_bus_clk(void);
> +void tlb_set(u32 mas0, u32 mas1, u32 mas2, u32 mas3);
> +phys_size_t fixed_sdram (void);
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void putc(char c)
> +{
> +	if (c == '\n')
> +		NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), '\r');
> +
> +	NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), c);
> +}
> +
> +void board_init_f(ulong bootflag)
> +{
> +	volatile ccsr_local_ecm_t *ecm = (void *) 
> (CONFIG_SYS_MPC85xx_ECM_ADDR);
> +	u32 mas0, mas1, mas2, mas3;
> +
> +	/* init serial port */
> +	NS16550_init((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500),
> +				get_bus_clk() / 16 / CONFIG_BAUDRATE);
> +	puts("NAND boot... ");
> +	init_timebase();
> +
> +	/* set TLB1[8] for DDR mapping */
> +	mas0 = FSL_BOOKE_MAS0(1, 8, 0);
> +	mas1 = FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G);
> +	mas2 = FSL_BOOKE_MAS2(0, 0);
> +	mas3 = FSL_BOOKE_MAS3(0, 0, MAS3_SX | MAS3_SW | MAS3_SR);
> +	tlb_set(mas0, mas1, mas2, mas3);
> +
> +	/* set LAW0 for DDR access */
> +	out_be32(&ecm->lawbar0, 0);
> +	out_be32(&ecm->lawar0, LAWAR_EN | (LAW_TRGT_IF_DDR << 20)
> +					| LAW_SIZE_512M);

we should use the last law not the first one in general.

>
> +	/* init DDR memory controller */
> +	fixed_sdram();
> +
> +	/* relocate the first bootstrap */
> +	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
> +		      CONFIG_SYS_NAND_U_BOOT_RELOC);
> +}
> +
> +void board_init_r(gd_t *gd, ulong dest_addr)
> +{
> +	nand_boot();
> +}

This code is part of the first stage (first 4k?) or second stage loader?

what is the entry point of the second stage loader?

- k


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