[U-Boot] [PATCH 12/12 v2] ARM: OMAP3: Add Overo board
dirk.behme at googlemail.com
dirk.behme at googlemail.com
Fri Oct 3 12:42:40 CEST 2008
Subject: [PATCH 12/12 v2] ARM: OMAP3: Add Overo board
From: Dirk Behme <dirk.behme at gmail.com>
Add Overo board
Signed-off-by: Dirk Behme <dirk.behme at gmail.com>
---
Changes in version v2:
- Rebase against u-boot-arm.git next (CFG vs. CONFIG changes)
Makefile | 3
board/omap3/overo/Makefile | 46 ++++++
board/omap3/overo/config.mk | 12 +
board/omap3/overo/overo.c | 119 +++++++++++++++++
board/omap3/overo/u-boot.lds | 63 +++++++++
include/configs/omap3_overo.h | 283 ++++++++++++++++++++++++++++++++++++++++++
6 files changed, 526 insertions(+)
Index: u-boot-arm/board/omap3/overo/Makefile
===================================================================
--- /dev/null
+++ u-boot-arm/board/omap3/overo/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := overo.o
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
Index: u-boot-arm/board/omap3/overo/config.mk
===================================================================
--- /dev/null
+++ u-boot-arm/board/omap3/overo/config.mk
@@ -0,0 +1,12 @@
+# Overo uses OMAP3 (ARM-CortexA8) cpu
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
+
+
Index: u-boot-arm/board/omap3/overo/overo.c
===================================================================
--- /dev/null
+++ u-boot-arm/board/omap3/overo/overo.c
@@ -0,0 +1,119 @@
+/*
+ * Maintainer : Steve Sakoman <steve at sakoman.com>
+ *
+ * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
+ * Richard Woodruff <r-woodruff2 at ti.com>
+ * Syed Mohammed Khasim <khasim at ti.com>
+ * Sunil Kumar <sunilsaini05 at gmail.com>
+ * Shashi Ranjan <shashiranjanmca05 at gmail.com>
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+
+const omap3_sysinfo sysinfo = {
+ SDP_3430_V1,
+ SDP_3430_V2,
+ "3503",
+ "Gumstix Overo board",
+};
+
+/******************************************************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************************************************/
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OVERO;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/******************************************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ *****************************************************************************/
+int misc_init_r(void)
+{
+
+ unsigned char byte;
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+ /* set vaux2 to 2.8V */
+ byte = 0x20;
+ i2c_write(0x4B, 0x76, 1, &byte, 1);
+ byte = 0x09;
+ i2c_write(0x4B, 0x79, 1, &byte, 1);
+
+ /* set vaux3 to 2.8V */
+ byte = 0x20;
+ i2c_write(0x4B, 0x7A, 1, &byte, 1);
+ byte = 0x03;
+ i2c_write(0x4B, 0x7D, 1, &byte, 1);
+
+ /* set vpll2 to 1.8V */
+ byte = 0xE0;
+ i2c_write(0x4B, 0x8E, 1, &byte, 1);
+ byte = 0x05;
+ i2c_write(0x4B, 0x91, 1, &byte, 1);
+
+ /* set VDAC to 1.8V */
+ byte = 0x20;
+ i2c_write(0x4B, 0x96, 1, &byte, 1);
+ byte = 0x03;
+ i2c_write(0x4B, 0x99, 1, &byte, 1);
+
+ byte = 0x33;
+ i2c_write(0x4A, 0xEE, 1, &byte, 1);
+
+ *((uint *) 0x49058034) = 0xFFFFFAF9;
+ *((uint *) 0x49056034) = 0x0F9F0FFF;
+ *((uint *) 0x49058094) = 0x00000506;
+ *((uint *) 0x49056094) = 0xF060F000;
+
+ return 0;
+}
+
+/******************************************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ *****************************************************************************/
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT_OVERO();
+}
+
Index: u-boot-arm/board/omap3/overo/u-boot.lds
===================================================================
--- /dev/null
+++ u-boot-arm/board/omap3/overo/u-boot.lds
@@ -0,0 +1,63 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm_cortexa8/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
+ __exidx_start = .;
+ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+ __exidx_end = .;
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
Index: u-boot-arm/include/configs/omap3_overo.h
===================================================================
--- /dev/null
+++ u-boot-arm/include/configs/omap3_overo.h
@@ -0,0 +1,283 @@
+/*
+ * Configuration settings for the Gumstix Overo board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_OVERO 1 /* working with overo */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_MMC 1
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_DOS_PARTITION 1
+
+/* commands to include */
+
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+
+#define CONFIG_CMD_AUTOSCRIPT /* autoscript support */
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_ECHO /* echo arguments */
+#define CONFIG_CMD_ENV /* saveenv */
+#define CONFIG_CMD_ITEST /* Integer (and string) test */
+#define CONFIG_CMD_LOADB /* loadb */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC /* misc functions like sleep etc*/
+#define CONFIG_CMD_RUN /* run command in env variable */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address to access nand at CS0 */
+#define CONFIG_SYS_NAND_WIDTH_16
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define NAND_ALLOW_ERASE_ALL
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+#define NAND_NO_RB 1
+#define CONFIG_SYS_NAND_WP
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_BOOTCOMMAND "mmcinit; fatload mmc 0 82000000 uImage; bootm 82000000"
+
+#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootdelay=1"
+
+#define CONFIG_NETMASK 255.255.254.0
+#define CONFIG_IPADDR 128.247.77.90
+#define CONFIG_SERVERIP 128.247.77.158
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT "Overo # "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0+0x01F00000) /* 31MB */
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */
+
+/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define V_PVT 7
+
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
+#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
+#define CONFIG_SYS_HZ ((V_SCLK)/(2 << CONFIG_SYS_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE SZ_128K /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M
+#define PISMO1_NOR_SIZE GPMC_SIZE_64M
+
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
+#define DBG_MPDB_SIZE GPMC_SIZE_16M
+#define PISMO2_SIZE 0
+
+#define CONFIG_SYS_MAX_FLASH_SECT (520) /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
+
+#define PHYS_FLASH_SIZE_SDPV2 SZ_128M
+#define PHYS_FLASH_SIZE SZ_32M
+
+#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#define PHYS_FLASH_SECT_SIZE boot_flash_sec
+/* Dummy declaration of flash banks to get compilation right */
+#define CONFIG_SYS_FLASH_BANKS_LIST {0, 0}
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at start of flash */
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND 1
+#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
+#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS+CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS /* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+#define ENV_IS_VARIABLE 1
+
+#ifndef __ASSEMBLY__
+extern unsigned int nand_cs_base;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+
+#define WRITE_NAND_COMMAND(d, adr)\
+ __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD))
+#define WRITE_NAND_ADDRESS(d, adr)\
+ __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR))
+#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT))
+#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT))
+
+/* Other NAND Access APIs */
+#define NAND_WP_OFF()\
+ do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
+#define NAND_WP_ON()\
+ do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand) udelay(10)
+
+#endif /* __CONFIG_H */
Index: u-boot-arm/Makefile
===================================================================
--- u-boot-arm.orig/Makefile
+++ u-boot-arm/Makefile
@@ -2722,6 +2722,9 @@ omap3_beagle_config : unconfig
omap3_evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm omap3 omap3
+omap3_overo_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo omap3 omap3
+
#########################################################################
## XScale Systems
#########################################################################
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