[U-Boot] [PATCH 19/24] FSL DDR: Convert STXSSA to new DDR code.

[Wolfgang Denk]

Dear Kumar,

In message <1219817457-7432-19-git-send-email-galak at kernel.crashing.org> you wrote:
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> ---
>  board/stxssa/Makefile    |    9 ++++--
>  board/stxssa/ddr.c       |   70 ++++++++++++++++++++++++++++++++++++++++++++++
>  board/stxssa/stxssa.c    |    6 +++-
>  board/stxssa/u-boot.lds  |    1 -
>  include/configs/stxssa.h |   30 +++++++++++--------
>  5 files changed, 98 insertions(+), 18 deletions(-)
>  create mode 100644 board/stxssa/ddr.c

How much of flexibility can be expected from the new DDR  code?  When
you  submitted  this  patch, I verified that it works in the standard
configuration (with a 256 MB RAM module). Should it  also  work  with
other configurations, say, with a 512 MB or a 1 GB module?

If I try it out, booting hangs here:

	U-Boot 2008.10-rc3-00009-gf7a35a6 (Oct 18 2008 - 18:21:52)

	CPU:   8541E, Version: 1.1, (0x807a0011)
	Core:  E500, Version: 2.0, (0x80200020)
	Clock Configuration:
	       CPU: 660 MHz, CCB: 264 MHz,
	       DDR: 132 MHz (264 MT/s data rate), LBC:  66 MHz
	CPM:   264 Mhz
	L1:    D-cache 32 kB enabled
	       I-cache 32 kB enabled
	Board: Silicon Tx GPPP SSA Board
	I2C:   ready
	DRAM:  512 MB

or:

	U-Boot 2008.10-rc3-00009-gf7a35a6 (Oct 18 2008 - 18:21:52)

	CPU:   8541E, Version: 1.1, (0x807a0011)
	Core:  E500, Version: 2.0, (0x80200020)
	Clock Configuration:
	       CPU: 660 MHz, CCB: 264 MHz,
	       DDR: 132 MHz (264 MT/s data rate), LBC:  66 MHz
	CPM:   264 Mhz
	L1:    D-cache 32 kB enabled
	       I-cache 32 kB enabled
	Board: Silicon Tx GPPP SSA Board
	I2C:   ready
	DRAM:   1 GB

I.e., the size gets detected correctly, but then it hangs.

I know that the old code did not support other memory  configurations;
should these work now with the new DDR code?

Best regards,

Wolfgang Denk

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