[U-Boot] MPC8567 - TEXT BASE boot rom question... Half the message was missing.. trying again..

[Scott Wood]

Bob Winslow wrote:
> I guess I don't understand TEXT_BASE very well..  and how it relates to
> the boot location:
> 
> From the manual:
>           4.4.3.3 Boot ROM Location
>                 The MPC8568E defines the default boot ROM address range
> to be 8 Mbytes at address 0x0_FF80_0000
>                 to 0x0_FFFF_FFFF. However, which peripheral interface
> handles these boot ROM accesses can be
>                 selected at power on.
> 
> What do I need to change to get a uboot image for the rom of reasonable
> size(say 512k instead of the 4meg)???  I have tried to change
> the value of TEXT_BASE to (xFFF8_0000) in the config.mk file(and other
> entries) but I must not be doing something else right.. 

What specifically happened when you tried changing TEXT_BASE?

> Any
> suggestions/help would
> be greatly appreciated!!   Am I writng the u-boot.bin to the wrong
> location in the flash when it is 512k?

You should write it to the end of flash.

>  Below is the relevant info from the files I think:
> 
> Thanks for your help in advance!
> 
> Bob
> 
> 
> *********** config.mk file
> 
> TEXT_BASE = 0xffc00000

The size of your image is going to be RESET_VECTOR_ADDRESS - TEXT_BASE + 
4.  Note that TEXT_BASE/RESET_VECTOR_ADDRESS should be set to the 
appropriate offset from where u-boot puts the flash.  This isn't 
necessarily where the hardware maps the flash on power-on, though from 
your board config it doesn't look like you move it.

> ********** from the include/configs/sevis8567.h file
> 
> /*
>  * Base addresses -- Note these are effective addresses where the
>  * actual resources get mapped (not physical addresses)
>  */
> #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR
> Default */
> #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated
> CCSRBAR */
> #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr
> of CCSRBAR */
> #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses
> CONFIG_SYS_IMMR */
> #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system
> memory*/
> #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
> #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of
> FLASH 8M */

4M flash or 8M?

> #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH_BASE
> 
> /*Chip select 0 - Flash*/
> #define CONFIG_SYS_BR0_PRELIM           0xfe001001
> #define CONFIG_SYS_OR0_PRELIM           0xfe006ff7

This is configuring the flash window for 32M...  It should be harmless, 
though -- the flash contents should just repeat within that window.

> ****************  from board/sevis/law.c
> struct law_entry law_table[] = {
>         SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
> 
>         /* LBC window  */
>         SET_LAW(CONFIG_SYS_LBC_CPLD_BASE,  LAW_SIZE_16M, LAW_TRGT_IF_LBC),
>         SET_LAW(CONFIG_SYS_LBC_E1_IF_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
>         SET_LAW(CONFIG_SYS_LBC_DSP_BASE,   LAW_SIZE_16M, LAW_TRGT_IF_LBC),
>         SET_LAW(CONFIG_SYS_LBC_FPGA_BASE,  LAW_SIZE_16M, LAW_TRGT_IF_LBC),
>         SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),

This looks like a problem -- you're setting the flash LAW to be only 
16M, but the window is 32M...  Either change 
TEXT_BASE/RESET_VECTOR_ADDRESS to be within the LAW, or extend/move the LAW.

-Scott