[U-Boot] [PATCH 3/3] mpc83xx: Add PCI-E support for MPC837XEMDS boards

[Liu Dave]

> +	/* Deassert the resets in the control register */
> +	out_be32(&sysconf->pecr1, 0xE0008000);
> +	if (!pex2)
> +		out_be32(&sysconf->pecr2, 0xE0008000);
> +	udelay(2000);
> +
> +	/* Configure PCI Express Local Access Windows */
> +	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
> +	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
> +
> +	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
> +	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
> +
> +	if (pex2)
> +		fsl_setup_serdes(CONFIG_FSL_SERDES2, 
> FSL_SERDES_PROTO_PEX_X2,
> +				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
> +	else
> +		fsl_setup_serdes(CONFIG_FSL_SERDES2, 
> FSL_SERDES_PROTO_PEX,
> +				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
> +

Umm, The serdes initialization should be finished before negated the
reset signal
according to the UM.
So, it is safe to move the serdes initialization before the
out_be32(pecr1/2);


> +#define CONFIG_SYS_PCIE1_BASE		0xA0000000
> +#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
> +#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000

Why did you keep the cfg window as 128MB?
Did you consider the compitable with FSL BSP?

> +#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
> +#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
> +#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
> +#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
> +#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
> +#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
> +
> +#define CONFIG_SYS_PCIE2_BASE		0xC0000000
> +#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
> +#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000

same