[U-Boot] TSEC ethernet controller problems (crc errors/ corruption)

[Liu Dave-R63238]

> Over the weekend we performed some hardware modifications
> on our boards with their troublesome gigabit interfaces.
> 
> We performed a couple of tests, one of which may be
> the solution to our problem.
> 
> 1) Modified the value of the series termination of EC_GTX_CLK125
> 
>     The PHY drives a 125MHz clock signal to the PowerPC
>     (EC_GTX_CLK125 signal) when operating in gigabit ethernet
>     mode.
> 
>     Our schematic used a 33-Ohm series termination on this
>     125MHz signal, but we had used 22-Ohms for all other series
>     terminations. The MDS board also uses 22-Ohms series
>     terminations.
> 
>     We replaced the 33-ohm termination with 22-ohms ... and
>     things started working. We looked at the 125MHz signal at
>     the destination pin on the BGA of the PowerPC using
>     a high-bandwidth scope (2GHz LeCroy) for both 22-Ohms
>     termination and 33-Ohms, and there is a slight
>     difference in waveform shape, but no obvious ringing,
>     or steps in the clock edges that might suggest
>     transmission line reflections.
> 
>     The fact that we only ever observed errors in gigabit
>     mode, that the PHY never reports any errors,
>     that EC_GTX_CLK125 is only used in gigabit mode,
>     and that the data errors looked like a FIFO clocking
>     issue, is consistent with the error being related to
>     the quanlity of the EC_GTX_CLK125 signal.
> 
>     I'm not ready to claim success, as I need to make the
>     change on other boards ... but its very encouraging!

Good news, Dave.
Sure, we need to keep the imdependence matching.
change the series resister.
Anyway, I strong recommand you to check if the signal
of GMII interface meet the H/W spec of 8349EA.

 
> 2) Frequency accuracy testing
> 
>     We replaced the PHY 125MHz clock source (an onboard
>     oscillator) with a frequency synthesizer driven into
>     a buffer (to create a 3.3V logic level clock).
> 
>     The frequency was adjusted to 124.90MHz, 124.95MHz,
>     125.00MHz, 125.05MHz, and 125.10MHz. Errors were
>     generated for the +/-0.1MHz cases, but things worked
>     fine for the +/-0.05MHz offsets.
> 
>     So the PHY is tolerant of frequency errors in the
>     oscillator.
> 
>     (This test was performed after the series termination
>      had been changed).
> 
> 
> Ira is going to boot the working board with Linux and
> perform some network stress tests.
> 
> I'll modify some other boards, and we'll tests those too.
> 
> Cheers,
> Dave
> 
> 
> 
>