[U-Boot] [PATCH 1/6] S5PC100: Samsung S5PC100 SoC support
HeungJun Kim
riverful.kim at gmail.com
Thu Jun 25 10:05:13 CEST 2009
S5PC100 processor is ARM Cortex A8 Processor SoC
and SMDKC100 Board use this.
So, this patch tested on SMDKC100 Board.
I'll send 6 patch for working on SMDKC100 Board including this.
But, this patch make the change to ARM Cortex A8 specific code
like a cpu/arm_cortexa8/cpu.c, start.S.
So, I wanna be reviewed to know how to contribute this whole patch.
CC: Dirk Behme <dirk.behme at googlemail.com>
Signed-off-by: HeungJun, Kim <riverful.kim at samsung.com>
---
It includes the following :
- Samsung S5PC100 SoC specific source codes
- Samsung S5PC100 SoC specific header files
- modify ARM Cortex A8 cpu.c, start.S
cpu/arm_cortexa8/cpu.c | 80 +---
cpu/arm_cortexa8/s5pc100/Makefile | 48 +++
cpu/arm_cortexa8/s5pc100/config.mk | 36 ++
cpu/arm_cortexa8/s5pc100/speed.c | 186 +++++++++
cpu/arm_cortexa8/s5pc100/timer.c | 223 ++++++++++
cpu/arm_cortexa8/start.S | 23 +
include/asm-arm/arch-s5pc100/clock-others.h | 33 ++
include/asm-arm/arch-s5pc100/cpu.h | 379 +++++++++++++++++
include/asm-arm/arch-s5pc100/gpio.h | 580 +++++++++++++++++++++++++++
include/asm-arm/arch-s5pc100/hardware.h | 63 +++
include/asm-arm/arch-s5pc100/map-base.h | 19 +
include/asm-arm/arch-s5pc100/sys_proto.h | 30 ++
include/asm-arm/arch-s5pc100/uart.h | 68 ++++
include/asm-arm/arch-s5pc100/watchdog.h | 16 +
include/s5pc1xx-onenand.h | 105 +++++
15 files changed, 1828 insertions(+), 61 deletions(-)
create mode 100644 cpu/arm_cortexa8/s5pc100/Makefile
create mode 100644 cpu/arm_cortexa8/s5pc100/config.mk
create mode 100644 cpu/arm_cortexa8/s5pc100/speed.c
create mode 100644 cpu/arm_cortexa8/s5pc100/timer.c
create mode 100644 include/asm-arm/arch-s5pc100/clock-others.h
create mode 100644 include/asm-arm/arch-s5pc100/cpu.h
create mode 100644 include/asm-arm/arch-s5pc100/gpio.h
create mode 100644 include/asm-arm/arch-s5pc100/hardware.h
create mode 100644 include/asm-arm/arch-s5pc100/map-base.h
create mode 100644 include/asm-arm/arch-s5pc100/sys_proto.h
create mode 100644 include/asm-arm/arch-s5pc100/uart.h
create mode 100644 include/asm-arm/arch-s5pc100/watchdog.h
create mode 100644 include/s5pc1xx-onenand.h
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 6fd07d0..95e8523 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -37,11 +37,28 @@
#include <asm/system.h>
#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
+void l2_cache_disable(void);
+#endif
+
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
#endif
static void cache_flush(void);
+int cpu_init(void)
+{
+ /*
+ * setup up stacks if necessary
+ */
+#ifdef CONFIG_USE_IRQ
+ IRQ_STACK_START =
+ _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
+ FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+ return 0;
+}
+
int cleanup_before_linux(void)
{
unsigned int i;
@@ -63,7 +80,7 @@ int cleanup_before_linux(void)
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
- l2cache_disable();
+ l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
@@ -78,65 +95,6 @@ int cleanup_before_linux(void)
return 0;
}
-void l2cache_enable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() >= CPU_3XX_ES20) {
- __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
- __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__("mov %0, r12":"=r"(j));
- __asm__ __volatile__("mov %0, r0":"=r"(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__("mov r12, #0x3");
- __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
- __asm__ __volatile__("orr r0, r0, #0x2");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- __asm__ __volatile__("mov r0, %0":"=r"(i));
- __asm__ __volatile__("mov r12, %0":"=r"(j));
- }
-
-}
-
-void l2cache_disable()
-{
- unsigned long i;
- volatile unsigned int j;
-
- /* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() >= CPU_3XX_ES20) {
- __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
- __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
- } else {
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__("mov %0, r12":"=r"(j));
- __asm__ __volatile__("mov %0, r0":"=r"(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__("mov r12, #0x3");
- __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
- __asm__ __volatile__("bic r0, r0, #0x2");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- __asm__ __volatile__("mov r0, %0":"=r"(i));
- __asm__ __volatile__("mov r12, %0":"=r"(j));
- }
-}
-
static void cache_flush(void)
{
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
diff --git a/cpu/arm_cortexa8/s5pc100/Makefile
b/cpu/arm_cortexa8/s5pc100/Makefile
new file mode 100644
index 0000000..511a8dc
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc100/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS-y = timer.o
+COBJS-$(CONFIG_S5PC100) += speed.o
+
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm_cortexa8/s5pc100/config.mk
b/cpu/arm_cortexa8/s5pc100/config.mk
new file mode 100644
index 0000000..e05d7ae
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc100/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v6.
+PLATFORM_CPPFLAGS += -march=armv5t
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+ $(call cc-option,-malignment-traps,))
diff --git a/cpu/arm_cortexa8/s5pc100/speed.c b/cpu/arm_cortexa8/s5pc100/speed.c
new file mode 100644
index 0000000..c5768f8
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc100/speed.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2009
+ * Inki Dae, SAMSUNG Electronics, <inki.dae at samsung.com>
+ * Heungjun Kim, SAMSUNG Electronics, <riverful.kim at samsung.com>
+ * Minkyu Kang, SAMSUNG Electronics, <mk7.kang at samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This code should work for both the S3C2400 and the S3C2410
+ * as they seem to have the same PLL and clock machinery inside.
+ * The different address mapping is handled by the s3c24xx.h files below.
+ */
+
+#include <common.h>
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+
+/* ------------------------------------------------------------------------- */
+/*
+ * NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+ ulong r, m, p, s, mask;
+
+ switch (pllreg) {
+ case APLL:
+ r = S5P_APLL_CON_REG;
+ break;
+ case MPLL:
+ r = S5P_MPLL_CON_REG;
+ break;
+ case EPLL:
+ r = S5P_EPLL_CON_REG;
+ break;
+ case HPLL:
+ r = S5P_HPLL_CON_REG;
+ break;
+ default:
+ hang();
+ }
+
+ if (pllreg == APLL)
+ mask = 0x3ff;
+ else
+ mask = 0x0ff;
+
+ m = (r >> 16) & mask;
+ p = (r >> 8) & 0x3f;
+ s = r & 0x7;
+
+ return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
+}
+
+/* return ARMCORE frequency */
+ulong get_ARMCLK(void)
+{
+ ulong div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio, arm_ratio;;
+
+ div = S5P_CLK_DIV0_REG;
+ /* ARM_RATIO: [6:4] */
+ arm_ratio = (div >> 4) & 0x7;
+ /* APLL_RATIO: [0] */
+ apll_ratio = div & 0x1;
+
+ dout_apll = get_PLLCLK(APLL) / (apll_ratio + 1);
+ armclk = dout_apll / (arm_ratio + 1);
+
+ return armclk;
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+ return get_PLLCLK(APLL);
+}
+
+/* return MCLK frequency */
+ulong get_MCLK(void)
+{
+ return get_PLLCLK(MPLL);
+}
+
+/* return HCLKD0 frequency */
+ulong get_HCLK(void)
+{
+ ulong hclkd0;
+ uint div, d0_bus_ratio;
+
+ div = S5P_CLK_DIV0_REG;
+ /* D0_BUS_RATIO: [10:8] */
+ d0_bus_ratio = (div >> 8) & 0x7;
+
+ hclkd0 = get_ARMCLK() / (d0_bus_ratio + 1);
+
+ return hclkd0;
+}
+
+/* return PCLKD0 frequency */
+ulong get_PCLKD0(void)
+{
+ ulong pclkd0;
+ uint div, pclkd0_ratio;
+
+ div = S5P_CLK_DIV0_REG;
+ /* PCLKD0_RATIO: [14:12] */
+ pclkd0_ratio = (div >> 12) & 0x7;
+
+ pclkd0 = get_HCLK() / (pclkd0_ratio + 1);
+
+ return pclkd0;
+}
+
+/* return PCLKD1 frequency */
+ulong get_PCLK(void)
+{
+ ulong d1_bus, pclkd1;
+ uint div, d1_bus_ratio, pclkd1_ratio;
+
+ div = S5P_CLK_DIV1_REG;
+ /* D1_BUS_RATIO: [14:12] */
+ d1_bus_ratio = (div >> 12) & 0x7;
+ /* PCLKD1_RATIO: [18:16] */
+ pclkd1_ratio = (div >> 16) & 0x7;
+
+ /* ASYNC Mode */
+ d1_bus = get_PLLCLK(MPLL) / (d1_bus_ratio + 1);
+ pclkd1 = d1_bus / (pclkd1_ratio + 1);
+
+ return pclkd1;
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+ return get_PLLCLK(EPLL);
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ unsigned int pid = __REG(S5P_PRO_ID);
+
+ pid >>= 12;
+ pid &= 0x00fff;
+
+ printf("CPU:\tS5PC%x@%luMHz\n", pid, get_ARMCLK() / 1000000);
+ printf("\tFclk = %luMHz, HclkD0 = %luMHz, PclkD0 = %luMHz,"
+ " PclkD1 = %luMHz\n",
+ get_FCLK() / 1000000, get_HCLK() / 1000000,
+ get_PCLKD0() / 1000000, get_PCLK() / 1000000);
+
+ return 0;
+}
+#endif
+
diff --git a/cpu/arm_cortexa8/s5pc100/timer.c b/cpu/arm_cortexa8/s5pc100/timer.c
new file mode 100644
index 0000000..0864600
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc100/timer.c
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger at sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu at sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin at arm.com>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
+ *
+ * (C) Copyright 2009
+ * Heungjun Kim, SAMSUNG Electronics, <riverful.kim at samsung.com>
+ * Inki Dae, SAMSUNG Electronics, <inki.dae at samsung.com>
+ * Minkyu Kang, SAMSUNG Electronics, <mk7.kang at samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
+#define MUX_DIV_2 (1) /* 1/2 period */
+#define MUX_DIV_4 (2) /* 1/4 period */
+#define MUX_DIV_8 (3) /* 1/8 period */
+#define MUX_DIV_16 (4) /* 1/16 period */
+#define MUX4_DIV_SHIFT 16
+
+#define TCON_TIMER4_SHIFT 20
+
+static ulong count_value;
+
+/* Internal tick units */
+static unsigned long long timestamp; /* Monotonic incrementing timer */
+static unsigned long lastdec; /* Last decremneter snapshot */
+
+/* macro to read the 16 bit timer */
+static inline ulong READ_TIMER(void)
+{
+ const s5pc1xx_timers_t *timers = (s5pc1xx_timers_t *) S5P_TIMER_BASE;
+
+ return timers->TCNTO4;
+}
+
+int timer_init(void)
+{
+ s5pc1xx_timers_t *timers = (s5pc1xx_timers_t *) S5P_TIMER_BASE;
+
+ /*
+ * @ PWM Timer 4
+ * Timer Freq(HZ) =
+ * PCLK / { (prescaler_value + 1) * (divider_value) }
+ */
+
+ /* set prescaler : 16 */
+ /* set divider : 2 */
+ timers->TCFG0 = (PRESCALER_1 & 0xff) << 8;
+ timers->TCFG1 = (MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT;
+
+ if (count_value == 0) {
+
+ /* reset initial value */
+ /* count_value = 2085937.5(HZ) (per 1 sec)*/
+ count_value = get_PCLK() / ((PRESCALER_1 + 1) *
+ (MUX_DIV_2 + 1));
+
+ /* count_value / 100 = 20859.375(HZ) (per 10 msec) */
+ count_value = count_value / 100;
+ }
+
+ /* set count value */
+ timers->TCNTB4 = count_value;
+ lastdec = count_value;
+
+ /* auto reload & manual update */
+ timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) |
+ S5P_TCON4_AUTO_RELOAD | S5P_TCON4_UPDATE;
+
+ /* start PWM timer 4 */
+ timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) |
+ S5P_TCON4_AUTO_RELOAD | S5P_TCON4_ON;
+
+ timestamp = 0;
+
+ return 0;
+}
+
+
+/*
+ * timer without interrupts
+ */
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds */
+void udelay(unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ if (usec >= 1000) {
+ /*
+ * if "big" number, spread normalization
+ * to seconds
+ * 1. start to normalize for usec to ticks per sec
+ * 2. find number of "ticks" to wait to achieve target
+ * 3. finish normalize.
+ */
+ tmo = usec / 1000;
+ tmo *= CONFIG_SYS_HZ;
+ tmo /= 1000;
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ;
+ tmo /= (1000 * 1000);
+ }
+
+ /* get current timestamp */
+ tmp = get_timer(0);
+
+ /* if setting this fordward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastdec value */
+ /* else, set advancing stamp wake up time */
+ if ((tmo + tmp + 1) < tmp)
+ reset_timer_masked();
+ else
+ tmo += tmp;
+
+ /* loop till event */
+ while (get_timer_masked() < tmo)
+ ; /* nop */
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ /* current tick value */
+ ulong now = READ_TIMER();
+
+ if (lastdec >= now)
+ timestamp += lastdec - now;
+ else
+ timestamp += lastdec + count_value - now;
+
+ lastdec = now;
+
+ return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ /* We overrun in 100s */
+ return CONFIG_SYS_HZ * 100;
+}
+
+void reset_cpu(ulong ignored)
+{
+ unsigned int pid = __REG(S5P_PRO_ID);
+
+ pid >>= 12;
+ pid &= 0x00fff;
+ pid |= (0xC << 12);
+
+ __REG(S5P_SW_RST) = pid;
+
+ while (1) ;
+}
diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S
index 66b4820..da6eed7 100644
--- a/cpu/arm_cortexa8/start.S
+++ b/cpu/arm_cortexa8/start.S
@@ -34,6 +34,7 @@
.globl _start
_start: b reset
+#ifndef CONFIG_ONENAND_IPL
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -50,6 +51,9 @@ _not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
+#else
+ . = _start + 64
+#endif
.global _end_vect
_end_vect:
@@ -108,6 +112,7 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
+#ifndef CONFIG_ONENAND_IPL
#if (CONFIG_OMAP34XX)
/* Copy vectors to mask ROM indirect addr */
adr r0, _start @ r0 <- current position of code
@@ -131,11 +136,13 @@ next:
bl cpy_clk_code @ put dpll adjust code behind vectors
#endif /* NAND Boot */
#endif
+#endif /* CONFIG_ONENAND_IPL */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
+#ifndef CONFIG_ONENAND_IPL
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: @ relocate U-Boot to RAM
adr r0, _start @ r0 <- current position of code
@@ -154,18 +161,24 @@ copy_loop: @ copy 32 bytes at a time
cmp r0, r2 @ until source end addreee [r2]
ble copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
+#endif /* CONFIG_ONENAND_IPL */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
+#ifdef CONFIG_ONENAND_IPL
+ sub sp, r0, #128 @ leave 32 words for abort-stack
+#else
sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 @ leave 3 words for abort-stack
+#endif /* CONFIG_ONENAND_IPL */
and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d
+#ifndef CONFIG_ONENAND_IPL
/* Clear BSS (if any). Is below tx (watch load addr - need space) */
clear_bss:
ldr r0, _bss_start @ find start of bss segment
@@ -176,10 +189,15 @@ clbss_l:
cmp r0, r1 @ are we at the end yet
add r0, r0, #4 @ increment clear index pointer
bne clbss_l @ keep clearing till at end
+#endif /* CONFIG_ONENAND_IPL */
ldr pc, _start_armboot @ jump to C code
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
_start_armboot: .word start_armboot
+#endif
/*************************************************************************
@@ -218,6 +236,8 @@ cpu_init_crit:
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
+
+#ifndef CONFIG_ONENAND_IPL
/*
*************************************************************************
*
@@ -502,6 +522,7 @@ finished_inval:
ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
+#if (CONFIG_OMAP34XX)
.align 5
.global reset_cpu
reset_cpu:
@@ -514,3 +535,5 @@ _loop_forever:
b _loop_forever
rstctl:
.word PRM_RSTCTRL
+#endif
+#endif /* CONFIG_ONENAND_IPL */
diff --git a/include/asm-arm/arch-s5pc100/clock-others.h
b/include/asm-arm/arch-s5pc100/clock-others.h
new file mode 100644
index 0000000..35f1686
--- /dev/null
+++ b/include/asm-arm/arch-s5pc100/clock-others.h
@@ -0,0 +1,33 @@
+
+/*
+ * Clock control - Others
+ */
+#define S5P_OTHERS_REG_BASE(x) (S5P_PA_CLK_OTHERS + (x))
+#define S5P_OTHERS_BASE S5P_OTHERS_REG_BASE(0x0)
+#define S5P_SW_RST S5P_OTHERS_REG_BASE(0x0)
+#define S5P_ONENAND_RST S5P_OTHERS_REG_BASE(0x8)
+#define S5P_GENERAL_CTRL S5P_OTHERS_REG_BASE(0x100)
+#define S5P_GENERAL_STATUS S5P_OTHERS_REG_BASE(0x104)
+#define S5P_MEM_SYS_CFG S5P_OTHERS_REG_BASE(0x200)
+#define S5P_CAM_MUX_SEL S5P_OTHERS_REG_BASE(0x300)
+#define S5P_MIXER_OUT_SEL S5P_OTHERS_REG_BASE(0x304)
+#define S5P_LPMP3_MODE_SEL S5P_OTHERS_REG_BASE(0x308)
+#define S5P_MIPI_PHY_CON0 S5P_OTHERS_REG_BASE(0x400)
+#define S5P_MIPI_PHY_CON1 S5P_OTHERS_REG_BASE(0x414)
+#define S5P_HDMI_PHY_CON0 S5P_OTHERS_REG_BASE(0x420)
+
+#ifndef __ASSEMBLY__
+#define S5P_OTHERS_BASE_REG __REG(S5P_OTHERS_BASE)
+#define S5P_SW_RST_REG __REG(S5P_SW_RST)
+#define S5P_ONENAND_RST_REG __REG(S5P_ONENAND_RST)
+#define S5P_GENERAL_CTRL_REG __REG(S5P_GENERAL_CTRL)
+#define S5P_GENERAL_STATUS_REG __REG(S5P_GENERAL_STATUS)
+#define S5P_MEM_SYS_CFG_REG __REG(S5P_MEM_SYS_CFG)
+#define S5P_CAM_MUX_SEL_REG __REG(S5P_CAM_MUX_SEL)
+#define S5P_MIXER_OUT_SEL_REG __REG(S5P_MIXER_OUT_SEL)
+#define S5P_LPMP3_MODE_SEL_REG __REG(S5P_LPMP3_MODE_SEL)
+#define S5P_MIPI_PHY_CON0_REG __REG(S5P_MIPI_PHY_CON0)
+#define S5P_MIPI_PHY_CON1_REG __REG(S5P_MIPI_PHY_CON1)
+#define S5P_HDMI_PHY_CON0_REG __REG(S5P_HDMI_PHY_CON0)
+#endif /* __ASSENBLY__ */
+
diff --git a/include/asm-arm/arch-s5pc100/cpu.h
b/include/asm-arm/arch-s5pc100/cpu.h
new file mode 100644
index 0000000..6ec8656
--- /dev/null
+++ b/include/asm-arm/arch-s5pc100/cpu.h
@@ -0,0 +1,379 @@
+/*
+ * (C) Copyright 2009
+ * Samsung Electronics, <www.samsung.com/sec>
+ * Heungjun Kim <riverful.kim at samsung.com>
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#include <asm/hardware.h>
+
+#ifndef __S5PC100_H__
+#define __S5PC100_H__
+
+#define S5P_ADDR_BASE 0xe0000000
+#define S5P_ADDR(x) (S5P_ADDR_BASE + (x))
+
+#define S5P_PA_ID S5P_ADDR(0x00000000) /* Chip ID Base */
+#define S5P_PA_CLK S5P_ADDR(0x00100000) /* Clock Base */
+#define S5P_PA_PWR S5P_ADDR(0x00108000) /* Power Base */
+#define S5P_PA_CLK_OTHERS S5P_ADDR(0x00200000) /* Clock Others Base */
+#define S5P_PA_GPIO S5P_ADDR(0x00300000) /* GPIO Base */
+#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Vector Interrupt
Controller 0 */
+#define S5P_PA_VIC1 S5P_ADDR(0x04100000) /* Vector Interrupt
Controller 1 */
+#define S5P_PA_VIC2 S5P_ADDR(0x04200000) /* Vector Interrupt
Controller 2 */
+#define S5P_PA_DMC S5P_ADDR(0x06000000) /* Dram Memory Controller */
+#define S5P_PA_SROMC S5P_ADDR(0x07000000) /* SROM Controller */
+#define S5P_PA_WATCHDOG S5P_ADDR(0x0a200000) /* Watchdog Timer */
+#define S5P_PA_PWMTIMER S5P_ADDR(0x0a000000) /* PWM Timer */
+
+/*
+ * Chip ID
+ */
+#define S5P_ID(x) (S5P_PA_ID + (x))
+
+#define S5P_PRO_ID S5P_ID(0)
+#define S5P_OMR S5P_ID(4)
+
+/*
+ * Clock control
+ */
+#define S5P_CLKREG(x) (S5P_PA_CLK + (x))
+
+/* Clock Register */
+#define S5P_APLL_LOCK S5P_CLKREG(0x0)
+#define S5P_MPLL_LOCK S5P_CLKREG(0x4)
+#define S5P_EPLL_LOCK S5P_CLKREG(0x8)
+#define S5P_HPLL_LOCK S5P_CLKREG(0xc)
+
+#define S5P_APLL_CON S5P_CLKREG(0x100)
+#define S5P_MPLL_CON S5P_CLKREG(0x104)
+#define S5P_EPLL_CON S5P_CLKREG(0x108)
+#define S5P_HPLL_CON S5P_CLKREG(0x10c)
+
+#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
+#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
+#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
+#define S5P_CLK_SRC3 S5P_CLKREG(0x20c)
+
+#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
+#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
+#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
+#define S5P_CLK_DIV3 S5P_CLKREG(0x30c)
+#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
+
+#define S5P_CLK_OUT S5P_CLKREG(0x400)
+
+#define S5P_CLK_GATE_D00 S5P_CLKREG(0x500)
+#define S5P_CLK_GATE_D01 S5P_CLKREG(0x504)
+#define S5P_CLK_GATE_D02 S5P_CLKREG(0x508)
+
+#define S5P_CLK_GATE_D10 S5P_CLKREG(0x520)
+#define S5P_CLK_GATE_D11 S5P_CLKREG(0x524)
+#define S5P_CLK_GATE_D12 S5P_CLKREG(0x528)
+#define S5P_CLK_GATE_D13 S5P_CLKREG(0x530)
+#define S5P_CLK_GATE_D14 S5P_CLKREG(0x534)
+
+#define S5P_CLK_GATE_D20 S5P_CLKREG(0x540)
+
+#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x560)
+#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x564)
+
+#ifndef __ASSEMBLY__
+/* Clock Address */
+#define S5P_APLL_LOCK_REG __REG(S5P_APLL_LOCK)
+#define S5P_MPLL_LOCK_REG __REG(S5P_MPLL_LOCK)
+#define S5P_EPLL_LOCK_REG __REG(S5P_EPLL_LOCK)
+#define S5P_HPLL_LOCK_REG __REG(S5P_HPLL_LOCK)
+
+#define S5P_APLL_CON_REG __REG(S5P_APLL_CON)
+#define S5P_MPLL_CON_REG __REG(S5P_MPLL_CON)
+#define S5P_EPLL_CON_REG __REG(S5P_EPLL_CON)
+#define S5P_HPLL_CON_REG __REG(S5P_HPLL_CON)
+
+#define S5P_CLK_SRC0_REG __REG(S5P_CLK_SRC0)
+#define S5P_CLK_SRC1_REG __REG(S5P_CLK_SRC1)
+#define S5P_CLK_SRC2_REG __REG(S5P_CLK_SRC2)
+#define S5P_CLK_SRC3_REG __REG(S5P_CLK_SRC3)
+
+#define S5P_CLK_DIV0_REG __REG(S5P_CLK_DIV0)
+#define S5P_CLK_DIV1_REG __REG(S5P_CLK_DIV1)
+#define S5P_CLK_DIV2_REG __REG(S5P_CLK_DIV2)
+#define S5P_CLK_DIV3_REG __REG(S5P_CLK_DIV3)
+#define S5P_CLK_DIV4_REG __REG(S5P_CLK_DIV4)
+
+#define S5P_CLK_OUT_REG __REG(S5P_CLK_OUT)
+
+#define S5P_CLK_GATE_D00_REG __REG(S5P_CLK_GATE_D00)
+#define S5P_CLK_GATE_D01_REG __REG(S5P_CLK_GATE_D01)
+#define S5P_CLK_GATE_D02_REG __REG(S5P_CLK_GATE_D02)
+
+#define S5P_CLK_GATE_D10_REG __REG(S5P_CLK_GATE_D10)
+#define S5P_CLK_GATE_D11_REG __REG(S5P_CLK_GATE_D11)
+#define S5P_CLK_GATE_D12_REG __REG(S5P_CLK_GATE_D12)
+#define S5P_CLK_GATE_D13_REG __REG(S5P_CLK_GATE_D13)
+#define S5P_CLK_GATE_D14_REG __REG(S5P_CLK_GATE_D14)
+
+#define S5P_CLK_GATE_D20_REG __REG(S5P_CLK_GATE_D20)
+
+#define S5P_CLK_GATE_SCLK0_REG __REG(S5P_CLK_GATE_SCLK0)
+#define S5P_CLK_GATE_SCLK1_REG __REG(S5P_CLK_GATE_SCLK1)
+#endif /* __ASSENBLY__ */
+
+
+/*
+ * Power control
+ */
+#define S5P_PWRREG(x) (S5P_PA_PWR + (x))
+
+#define S5P_PWR_CFG S5P_PWRREG(0x0)
+#define S5P_EINT_WAKEUP_MASK S5P_PWRREG(0x04)
+#define S5P_NORMAL_CFG S5P_PWRREG(0x10)
+#define S5P_STOP_CFG S5P_PWRREG(0x14)
+#define S5P_SLEEP_CFG S5P_PWRREG(0x18)
+#define S5P_STOP_MEM_CFG S5P_PWRREG(0x1c)
+#define S5P_OSC_FREQ S5P_PWRREG(0x100)
+#define S5P_OSC_STABLE S5P_PWRREG(0x104)
+#define S5P_PWR_STABLE S5P_PWRREG(0x108)
+#define S5P_INTERNAL_PWR_STABLE S5P_PWRREG(0x110)
+#define S5P_CLAMP_STABLE S5P_PWRREG(0x114)
+#define S5P_OTHERS S5P_PWRREG(0x200)
+#define S5P_RST_STAT S5P_PWRREG(0x300)
+#define S5P_WAKEUP_STAT S5P_PWRREG(0x304)
+#define S5P_BLK_PWR_STAT S5P_PWRREG(0x308)
+#define S5P_INFORM0 S5P_PWRREG(0x400)
+#define S5P_INFORM1 S5P_PWRREG(0x404)
+#define S5P_INFORM2 S5P_PWRREG(0x408)
+#define S5P_INFORM3 S5P_PWRREG(0x40c)
+#define S5P_INFORM4 S5P_PWRREG(0x410)
+#define S5P_INFORM5 S5P_PWRREG(0x414)
+#define S5P_INFORM6 S5P_PWRREG(0x418)
+#define S5P_INFORM7 S5P_PWRREG(0x41c)
+#define S5P_DCGIDX_MAP0 S5P_PWRREG(0x500)
+#define S5P_DCGIDX_MAP1 S5P_PWRREG(0x504)
+#define S5P_DCGIDX_MAP2 S5P_PWRREG(0x508)
+#define S5P_DCGPERF_MAP0 S5P_PWRREG(0x50c)
+#define S5P_DCGPERF_MAP1 S5P_PWRREG(0x510)
+#define S5P_DVCIDX_MAP S5P_PWRREG(0x514)
+#define S5P_FREQ_CPU S5P_PWRREG(0x518)
+#define S5P_FREQ_DPM S5P_PWRREG(0x51c)
+#define S5P_DVSEMCLK_EN S5P_PWRREG(0x520)
+#define S5P_APLL_CON_L8 S5P_PWRREG(0x600)
+#define S5P_APLL_CON_L7 S5P_PWRREG(0x604)
+#define S5P_APLL_CON_L6 S5P_PWRREG(0x608)
+#define S5P_APLL_CON_L5 S5P_PWRREG(0x60c)
+#define S5P_APLL_CON_L4 S5P_PWRREG(0x610)
+#define S5P_APLL_CON_L3 S5P_PWRREG(0x614)
+#define S5P_APLL_CON_L2 S5P_PWRREG(0x618)
+#define S5P_APLL_CON_L1 S5P_PWRREG(0x61c)
+#define S5P_EM_CONTROL S5P_PWRREG(0x620)
+
+#define S5P_CLKDIV_IEM_L8 S5P_PWRREG(0x700)
+#define S5P_CLKDIV_IEM_L7 S5P_PWRREG(0x704)
+#define S5P_CLKDIV_IEM_L6 S5P_PWRREG(0x708)
+#define S5P_CLKDIV_IEM_L5 S5P_PWRREG(0x70c)
+#define S5P_CLKDIV_IEM_L4 S5P_PWRREG(0x710)
+#define S5P_CLKDIV_IEM_L3 S5P_PWRREG(0x714)
+#define S5P_CLKDIV_IEM_L2 S5P_PWRREG(0x718)
+#define S5P_CLKDIV_IEM_L1 S5P_PWRREG(0x71c)
+
+#define S5P_IEM_HPMCLK_DIV S5P_PWRREG(0x724)
+
+
+/*
+ * Vector Interrupt Controller
+ * : VIC0, VIC1, VIC2
+ */
+/* VIC0 */
+#define S5P_VIC0_BASE(x) (S5P_PA_VIC0 + (x))
+#define S5P_VIC1_BASE(x) (S5P_PA_VIC1 + (x))
+#define S5P_VIC2_BASE(x) (S5P_PA_VIC2 + (x))
+
+/* Vector Interrupt Offset */
+#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */
+#define VIC_FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */
+#define VIC_RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */
+#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */
+#define VIC_INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */
+#define VIC_INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */
+#define VIC_SOFTINT_OFFSET 0x18 /* Software Interrupt Register */
+#define VIC_SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */
+#define VIC_PROTECTION_OFFSET 0x20 /* Protection Enable Register */
+#define VIC_SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */
+#define VIC_PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for
Daisy Chain */
+#define VIC_INTADDRESS_OFFSET 0xf00 /* Vector Priority Register for
Daisy Chain */
+
+
+/*
+ * SROMC Controller
+ */
+/* DRAM Memory Controller */
+#define S5P_DMC_BASE(x) (S5P_PA_DMC + (x))
+/* SROMC Base */
+#define S5P_SROMC_BASE(x) (S5P_PA_SROMC + (x))
+/* SROMC offset */
+#define CONCONTROL_OFFSET 0x0 /* Controller Control Register */
+#define MEMCONTROL_OFFSET 0x04 /* Memory Control Register */
+#define MEMCONFIG0_OFFSET 0x08 /* Memory Chip0 Configuration Register */
+#define MEMCONFIG1_OFFSET 0x0c /* Memory Chip1 Configuration Register */
+#define DIRECTCMD_OFFSET 0x10 /* Memory Direct Command Register */
+#define PRECHCONFIG_OFFSET 0x14 /* Precharge Policy Configuration Register */
+#define PHYCONTROL0_OFFSET 0x18 /* PHY Control0 Register */
+#define PHYCONTROL1_OFFSET 0x1c /* PHY Control1 Register */
+#define PHYCONTROL2_OFFSET 0x20 /* PHY Control2 Register */
+#define PWRDNCONFIG_OFFSET 0x28 /* Dynamic Power Down Configuration Register */
+#define TIMINGAREF_OFFSET 0x30 /* AC Timing Register for SDRAM Auto Refresh */
+#define TIMINGROW_OFFSET 0x34 /* AC Timing Register for SDRAM Row */
+#define TIMINGDATA_OFFSET 0x38 /* AC Timing Register for SDRAM Data */
+#define TIMINGPOWER_OFFSET 0x3c /* AC Timing Register for Power Mode
of SDRAM */
+#define PHYSTATUS0_OFFSET 0x40 /* PHY Status Register 0 */
+#define PHYSTATUS1_OFFSET 0x44 /* PHY Status Register 1 */
+#define CHIP0STATUS_OFFSET 0x48 /* Memory Chip0 Status Register */
+#define CHIP1STATUS_OFFSET 0x4c /* Memory Chip1 Status Register */
+#define AREFSTATUS_OFFSET 0x50 /* Counter status Register for Auto Refresh */
+#define MRSTATUS_OFFSET 0x54 /* Memory Mode Registers Status Register */
+#define PHYTEST0_OFFSET 0x58 /* PHY Test Register 0 */
+#define PHYTEST1_OFFSET 0x5c /* PHY Test Register 1 */
+
+#define S5P_CONCONTROL S5P_DMC_BASE(CONCONTROL_OFFSET)
+#define S5P_MEMCONTROL S5P_DMC_BASE(MEMCONTROL_OFFSET)
+#define S5P_MEMCONFIG0 S5P_DMC_BASE(MEMCONFIG0_OFFSET)
+#define S5P_MEMCONFIG1 S5P_DMC_BASE(MEMCONFIG1_OFFSET)
+#define S5P_DIRECTCMD S5P_DMC_BASE(DIRECTCMD_OFFSET)
+#define S5P_PRECHCONFIG S5P_DMC_BASE(PRECHCONFIG_OFFSET)
+#define S5P_PHYCONTROL0 S5P_DMC_BASE(PHYCONTROL0_OFFSET)
+#define S5P_PHYCONTROL1 S5P_DMC_BASE(PHYCONTROL1_OFFSET)
+#define S5P_PHYCONTROL2 S5P_DMC_BASE(PHYCONTROL2_OFFSET)
+#define S5P_PWRDNCONFIG S5P_DMC_BASE(PWRDNCONFIG_OFFSET)
+#define S5P_TIMINGAREF S5P_DMC_BASE(TIMINGAREF_OFFSET)
+#define S5P_TIMINGROW S5P_DMC_BASE(TIMINGROW_OFFSET)
+#define S5P_TIMINGDATA S5P_DMC_BASE(TIMINGDATA_OFFSET)
+#define S5P_TIMINGPOWER S5P_DMC_BASE(TIMINGPOWER_OFFSET)
+#define S5P_PHYSTATUS0 S5P_DMC_BASE(PHYSTATUS0_OFFSET)
+#define S5P_PHYSTATUS1 S5P_DMC_BASE(PHYSTATUS1_OFFSET)
+#define S5P_CHIP0STATUS S5P_DMC_BASE(CHIP0STATUS_OFFSET)
+#define S5P_CHIP1STATUS S5P_DMC_BASE(CHIP1STATUS_OFFSET)
+#define S5P_AREFSTATUS S5P_DMC_BASE(AREFSTATUS_OFFSET)
+#define S5P_MRSTATUS S5P_DMC_BASE(MRSTATUS_OFFSET)
+#define S5P_PHYTEST0 S5P_DMC_BASE(PHYTEST0_OFFSET)
+#define S5P_PHYTEST1 S5P_DMC_BASE(PHYTEST1_OFFSET)
+
+
+/*
+ * PWM Timer
+ */
+#define S5P_PWMTIMER_BASE(x) (S5P_PA_PWMTIMER + (x))
+
+/* PWM timer offset */
+#define PWM_TCFG0_OFFSET 0x0
+#define PWM_TCFG1_OFFSET 0x04
+#define PWM_TCON_OFFSET 0x08
+#define PWM_TCNTB0_OFFSET 0x0c
+#define PWM_TCMPB0_OFFSET 0x10
+#define PWM_TCNTO0_OFFSET 0x14
+#define PWM_TCNTB1_OFFSET 0x18
+#define PWM_TCMPB1_OFFSET 0x1c
+#define PWM_TCNTO1_OFFSET 0x20
+#define PWM_TCNTB2_OFFSET 0x24
+#define PWM_TCMPB2_OFFSET 0x28
+#define PWM_TCNTO2_OFFSET 0x2c
+#define PWM_TCNTB3_OFFSET 0x30
+#define PWM_TCNTO3_OFFSET 0x38
+#define PWM_TCNTB4_OFFSET 0x3c
+#define PWM_TCNTO4_OFFSET 0x40
+#define PWM_TINT_CSTAT_OFFSET 0x44
+
+/* PWM timer register */
+#define S5P_PWM_TCFG0 S5P_PWMTIMER_BASE(PWM_TCFG0_OFFSET)
+#define S5P_PWM_TCFG1 S5P_PWMTIMER_BASE(PWM_TCFG1_OFFSET)
+#define S5P_PWM_TCON S5P_PWMTIMER_BASE(PWM_TCON_OFFSET)
+#define S5P_PWM_TCNTB0 S5P_PWMTIMER_BASE(PWM_TCNTB0_OFFSET)
+#define S5P_PWM_TCMPB0 S5P_PWMTIMER_BASE(PWM_TCMPB0_OFFSET)
+#define S5P_PWM_TCNTO0 S5P_PWMTIMER_BASE(PWM_TCNTO0_OFFSET)
+#define S5P_PWM_TCNTB1 S5P_PWMTIMER_BASE(PWM_TCNTB1_OFFSET)
+#define S5P_PWM_TCMPB1 S5P_PWMTIMER_BASE(PWM_TCMPB1_OFFSET)
+#define S5P_PWM_TCNTO1 S5P_PWMTIMER_BASE(PWM_TCNTO1_OFFSET)
+#define S5P_PWM_TCNTB2 S5P_PWMTIMER_BASE(PWM_TCNTB2_OFFSET)
+#define S5P_PWM_TCMPB2 S5P_PWMTIMER_BASE(PWM_TCMPB2_OFFSET)
+#define S5P_PWM_TCNTO2 S5P_PWMTIMER_BASE(PWM_TCNTO2_OFFSET)
+#define S5P_PWM_TCNTB3 S5P_PWMTIMER_BASE(PWM_TCNTB3_OFFSET)
+#define S5P_PWM_TCNTO3 S5P_PWMTIMER_BASE(PWM_TCNTO3_OFFSET)
+#define S5P_PWM_TCNTB4 S5P_PWMTIMER_BASE(PWM_TCNTB4_OFFSET)
+#define S5P_PWM_TCNTO4 S5P_PWMTIMER_BASE(PWM_TCNTO4_OFFSET)
+#define S5P_PWM_TINT_CSTAT S5P_PWMTIMER_BASE(PWM_TINT_CSTAT_OFFSET)
+
+/* PWM timer addressing */
+#define S5P_TIMER_BASE S5P_PWMTIMER_BASE(0x0)
+#define S5P_PWMTIMER_BASE_REG __REG(S5P_PWMTIMER_BASE(0x0))
+#define S5P_PWM_TCFG0_REG __REG(S5P_PWM_TCFG0)
+#define S5P_PWM_TCFG1_REG __REG(S5P_PWM_TCFG1)
+#define S5P_PWM_TCON_REG __REG(S5P_PWM_TCON)
+#define S5P_PWM_TCNTB0_REG __REG(S5P_PWM_TCNTB0)
+#define S5P_PWM_TCMPB0_REG __REG(S5P_PWM_TCMPB0)
+#define S5P_PWM_TCNTO0_REG __REG(S5P_PWM_TCNTO0)
+#define S5P_PWM_TCNTB1_REG __REG(S5P_PWM_TCNTB1)
+#define S5P_PWM_TCMPB1_REG __REG(S5P_PWM_TCMPB1)
+#define S5P_PWM_TCNTO1_REG __REG(S5P_PWM_TCNTO1)
+#define S5P_PWM_TCNTB2_REG __REG(S5P_PWM_TCNTB2)
+#define S5P_PWM_TCMPB2_REG __REG(S5P_PWM_TCMPB2)
+#define S5P_PWM_TCNTO2_REG __REG(S5P_PWM_TCNTO2)
+#define S5P_PWM_TCNTB3_REG __REG(S5P_PWM_TCNTB3)
+#define S5P_PWM_TCNTO3_REG __REG(S5P_PWM_TCNTO3)
+#define S5P_PWM_TCNTB4_REG __REG(S5P_PWM_TCNTB4)
+#define S5P_PWM_TCNTO4_REG __REG(S5P_PWM_TCNTO4)
+#define S5P_PWM_TINT_CSTAT_REG __REG(S5P_PWM_TINT_CSTAT)
+
+/* PWM timer value */
+#define S5P_TCON4_AUTO_RELOAD (1 << 22) /* Interval mode(Auto
Reload) of PWM Timer 4 */
+#define S5P_TCON4_UPDATE (1 << 21) /* Update TCNTB4 */
+#define S5P_TCON4_ON (1 << 20) /* start bit of PWM Timer 4 */
+
+#ifndef __ASSEMBLY__
+typedef struct s5pc1xx_timer {
+ volatile unsigned long TCFG0;
+ volatile unsigned long TCFG1;
+ volatile unsigned long TCON;
+ volatile unsigned long TCNTB0;
+ volatile unsigned long TCMPB0;
+ volatile unsigned long TCNTO0;
+ volatile unsigned long TCNTB1;
+ volatile unsigned long TCMPB1;
+ volatile unsigned long TCNTO1;
+ volatile unsigned long TCNTB2;
+ volatile unsigned long TCMPB2;
+ volatile unsigned long TCNTO2;
+ volatile unsigned long TCNTB3;
+ volatile unsigned long res1;
+ volatile unsigned long TCNTO3;
+ volatile unsigned long TCNTB4;
+ volatile unsigned long TCNTO4;
+ volatile unsigned long TINTCSTAT;
+} s5pc1xx_timers_t;
+#endif /* __ASSEMBLY__ */
+
+#include <asm/arch/uart.h>
+#include <asm/arch/watchdog.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clock-others.h>
+
+#endif /* __S5PC100_H__ */
+
+#endif /* _CPU_H */
diff --git a/include/asm-arm/arch-s5pc100/gpio.h
b/include/asm-arm/arch-s5pc100/gpio.h
new file mode 100644
index 0000000..bd49aaa
--- /dev/null
+++ b/include/asm-arm/arch-s5pc100/gpio.h
@@ -0,0 +1,580 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Heungjun Kim <riverful.kim at samsung.com>
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * GPIO
+ */
+
+/* GPIO Bank Base */
+#define S5P_GPIO_BASE(x) (S5P_PA_GPIO + (x))
+
+#define S5P_GPIO_A_REG(x) (S5P_GPIO_BASE(0x0) + (x))
+#define S5P_GPIO_B_REG(x) (S5P_GPIO_BASE(0x40) + (x))
+#define S5P_GPIO_C_REG(x) (S5P_GPIO_BASE(0x60) + (x))
+#define S5P_GPIO_D_REG(x) (S5P_GPIO_BASE(0x80) + (x))
+#define S5P_GPIO_E_REG(x) (S5P_GPIO_BASE(0xa0) + (x))
+#define S5P_GPIO_F_REG(x) (S5P_GPIO_BASE(0xe0) + (x))
+#define S5P_GPIO_G_REG(x) (S5P_GPIO_BASE(0x160) + (x))
+#define S5P_GPIO_I_REG(x) (S5P_GPIO_BASE(0x1e0) + (x))
+#define S5P_GPIO_J_REG(x) (S5P_GPIO_BASE(0x200) + (x))
+#define S5P_GPIO_K_REG(x) (S5P_GPIO_BASE(0x2a0) + (x))
+#define S5P_GPIO_L_REG(x) (S5P_GPIO_BASE(0x320) + (x))
+
+#define S5P_MP_REG(x) (S5P_GPIO_BASE(0x3c0) + (x))
+#define S5P_ETC_REG(x) (S5P_GPIO_BASE(0x4e0) + (x))
+
+#define S5P_GPIO_INT_CON_REG(x) (S5P_GPIO_BASE(0x700) + (x))
+#define S5P_GPIO_INT_FLTCON_REG(x) (S5P_GPIO_BASE(0x800) + (x))
+#define S5P_GPIO_INT_MASK_REG(x) (S5P_GPIO_BASE(0x900) + (x))
+#define S5P_GPIO_INT_PEND_REG(x) (S5P_GPIO_BASE(0xa00) + (x))
+#define S5P_GPIO_INT_PRIO_REG(x) (S5P_GPIO_BASE(0xb00) + (x))
+
+#define S5P_GPIO_H_REG(x) (S5P_GPIO_BASE(0xc00) + (x))
+
+#define S5P_WAKEUP_INT_CON(x) (S5P_GPIO_BASE(0xe00) + (x))
+#define S5P_WAKEUP_FLTINT_CON(x) (S5P_GPIO_BASE(0xe80) + (x))
+#define S5P_WAKEUP_INT_MASK(x) (S5P_GPIO_BASE(0xf00) + (x))
+#define S5P_WAKEUP_INT_PEND(x) (S5P_GPIO_BASE(0xf40) + (x))
+
+
+/* GPIO Offset */
+#define CON_OFFSET 0x0
+#define DAT_OFFSET 0x4
+#define PULL_OFFSET 0x8
+#define DRV_OFFSET 0xc
+#define PDNCON_OFFSET 0x10
+#define PDNPULL_OFFSET 0x14
+
+
+/* GPIO A Bank Base */
+#define S5P_GPIO_A0_BASE(x) (S5P_GPIO_A_REG(0x0) + (x))
+#define S5P_GPIO_A1_BASE(x) (S5P_GPIO_A_REG(0x20) + (x))
+
+#define S5P_GPIO_A0_CON S5P_GPIO_A0_BASE(CON_OFFSET)
+#define S5P_GPIO_A0_DAT S5P_GPIO_A0_BASE(DAT_OFFSET)
+#define S5P_GPIO_A0_PULL S5P_GPIO_A0_BASE(PULL_OFFSET)
+#define S5P_GPIO_A0_DRV S5P_GPIO_A0_BASE(DRV_OFFSET)
+#define S5P_GPIO_A0_PDNCON S5P_GPIO_A0_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_A0_PDNPUL S5P_GPIO_A0_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_A1_CON S5P_GPIO_A1_BASE(CON_OFFSET)
+#define S5P_GPIO_A1_DAT S5P_GPIO_A1_BASE(DAT_OFFSET)
+#define S5P_GPIO_A1_PULL S5P_GPIO_A1_BASE(PULL_OFFSET)
+#define S5P_GPIO_A1_DRV S5P_GPIO_A1_BASE(DRV_OFFSET)
+#define S5P_GPIO_A1_PDNCON S5P_GPIO_A1_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_A1_PDNPUL S5P_GPIO_A1_BASE(PDNPULL_OFFSET)
+
+/* GPIO B Bank Base */
+#define S5P_GPIO_B_BASE(x) (S5P_GPIO_B_REG(0x0) + (x))
+
+#define S5P_GPIO_B_CON S5P_GPIO_B_BASE(CON_OFFSET)
+#define S5P_GPIO_B_DAT S5P_GPIO_B_BASE(DAT_OFFSET)
+#define S5P_GPIO_B_PULL S5P_GPIO_B_BASE(PULL_OFFSET)
+#define S5P_GPIO_B_DRV S5P_GPIO_B_BASE(DRV_OFFSET)
+#define S5P_GPIO_B_PDNCON S5P_GPIO_B_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_B_PDNPUL S5P_GPIO_B_BASE(PDNPULL_OFFSET)
+
+/* GPIO C Bank Base */
+#define S5P_GPIO_C_BASE(x) (S5P_GPIO_C_REG(0x0) + (x))
+
+#define S5P_GPIO_C_CON S5P_GPIO_C_BASE(CON_OFFSET)
+#define S5P_GPIO_C_DAT S5P_GPIO_C_BASE(DAT_OFFSET)
+#define S5P_GPIO_C_PULL S5P_GPIO_C_BASE(PULL_OFFSET)
+#define S5P_GPIO_C_DRV S5P_GPIO_C_BASE(DRV_OFFSET)
+#define S5P_GPIO_C_PDNCON S5P_GPIO_C_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_C_PDNPUL S5P_GPIO_C_BASE(PDNPULL_OFFSET)
+
+/* GPIO D Bank Base */
+#define S5P_GPIO_D_BASE(x) (S5P_GPIO_D_REG(0x0) + (x))
+
+#define S5P_GPIO_D_CON S5P_GPIO_D_BASE(CON_OFFSET)
+#define S5P_GPIO_D_DAT S5P_GPIO_D_BASE(DAT_OFFSET)
+#define S5P_GPIO_D_PULL S5P_GPIO_D_BASE(PULL_OFFSET)
+#define S5P_GPIO_D_DRV S5P_GPIO_D_BASE(DRV_OFFSET)
+#define S5P_GPIO_D_PDNCON S5P_GPIO_D_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_D_PDNPUL S5P_GPIO_D_BASE(PDNPULL_OFFSET)
+
+/* GPIO E Bank Base */
+#define S5P_GPIO_E0_BASE(x) (S5P_GPIO_E_REG(0x0) + (x))
+#define S5P_GPIO_E1_BASE(x) (S5P_GPIO_E_REG(0x20) + (x))
+
+#define S5P_GPIO_E0_CON S5P_GPIO_E0_BASE(CON_OFFSET)
+#define S5P_GPIO_E0_DAT S5P_GPIO_E0_BASE(DAT_OFFSET)
+#define S5P_GPIO_E0_PULL S5P_GPIO_E0_BASE(PULL_OFFSET)
+#define S5P_GPIO_E0_DRV S5P_GPIO_E0_BASE(DRV_OFFSET)
+#define S5P_GPIO_E0_PDNCON S5P_GPIO_E0_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_E0_PDNPUL S5P_GPIO_E0_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_E1_CON S5P_GPIO_E1_BASE(CON_OFFSET)
+#define S5P_GPIO_E1_DAT S5P_GPIO_E1_BASE(DAT_OFFSET)
+#define S5P_GPIO_E1_PULL S5P_GPIO_E1_BASE(PULL_OFFSET)
+#define S5P_GPIO_E1_DRV S5P_GPIO_E1_BASE(DRV_OFFSET)
+#define S5P_GPIO_E1_PDNCON S5P_GPIO_E1_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_E1_PDNPUL S5P_GPIO_E1_BASE(PDNPULL_OFFSET)
+
+/* GPIO F Bank Base */
+#define S5P_GPIO_F0_BASE(x) (S5P_GPIO_F_REG(0x0) + (x))
+#define S5P_GPIO_F1_BASE(x) (S5P_GPIO_F_REG(0x20) + (x))
+#define S5P_GPIO_F2_BASE(x) (S5P_GPIO_F_REG(0x40) + (x))
+#define S5P_GPIO_F3_BASE(x) (S5P_GPIO_F_REG(0x60) + (x))
+
+#define S5P_GPIO_F0_CON S5P_GPIO_F0_BASE(CON_OFFSET)
+#define S5P_GPIO_F0_DAT S5P_GPIO_F0_BASE(DAT_OFFSET)
+#define S5P_GPIO_F0_PULL S5P_GPIO_F0_BASE(PULL_OFFSET)
+#define S5P_GPIO_F0_DRV S5P_GPIO_F0_BASE(DRV_OFFSET)
+#define S5P_GPIO_F0_PDNCON S5P_GPIO_F0_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_F0_PDNPUL S5P_GPIO_F0_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_F1_CON S5P_GPIO_F1_BASE(CON_OFFSET)
+#define S5P_GPIO_F1_DAT S5P_GPIO_F1_BASE(DAT_OFFSET)
+#define S5P_GPIO_F1_PULL S5P_GPIO_F1_BASE(PULL_OFFSET)
+#define S5P_GPIO_F1_DRV S5P_GPIO_F1_BASE(DRV_OFFSET)
+#define S5P_GPIO_F1_PDNCON S5P_GPIO_F1_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_F1_PDNPUL S5P_GPIO_F1_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_F2_CON S5P_GPIO_F2_BASE(CON_OFFSET)
+#define S5P_GPIO_F2_DAT S5P_GPIO_F2_BASE(DAT_OFFSET)
+#define S5P_GPIO_F2_PULL S5P_GPIO_F2_BASE(PULL_OFFSET)
+#define S5P_GPIO_F2_DRV S5P_GPIO_F2_BASE(DRV_OFFSET)
+#define S5P_GPIO_F2_PDNCON S5P_GPIO_F2_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_F2_PDNPUL S5P_GPIO_F2_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_F3_CON S5P_GPIO_F3_BASE(CON_OFFSET)
+#define S5P_GPIO_F3_DAT S5P_GPIO_F3_BASE(DAT_OFFSET)
+#define S5P_GPIO_F3_PULL S5P_GPIO_F3_BASE(PULL_OFFSET)
+#define S5P_GPIO_F3_DRV S5P_GPIO_F3_BASE(DRV_OFFSET)
+#define S5P_GPIO_F3_PDNCON S5P_GPIO_F3_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_F3_PDNPUL S5P_GPIO_F3_BASE(PDNPULL_OFFSET)
+
+/* GPIO G Bank Base */
+#define S5P_GPIO_G0_BASE(x) (S5P_GPIO_G_REG(0x0) + (x))
+#define S5P_GPIO_G1_BASE(x) (S5P_GPIO_G_REG(0x20) + (x))
+#define S5P_GPIO_G2_BASE(x) (S5P_GPIO_G_REG(0x40) + (x))
+#define S5P_GPIO_G3_BASE(x) (S5P_GPIO_G_REG(0x60) + (x))
+
+#define S5P_GPIO_G0_CON S5P_GPIO_G0_BASE(CON_OFFSET)
+#define S5P_GPIO_G0_DAT S5P_GPIO_G0_BASE(DAT_OFFSET)
+#define S5P_GPIO_G0_PULL S5P_GPIO_G0_BASE(PULL_OFFSET)
+#define S5P_GPIO_G0_DRV S5P_GPIO_G0_BASE(DRV_OFFSET)
+#define S5P_GPIO_G0_PDNCON S5P_GPIO_G0_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_G0_PDNPUL S5P_GPIO_G0_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_G1_CON S5P_GPIO_G1_BASE(CON_OFFSET)
+#define S5P_GPIO_G1_DAT S5P_GPIO_G1_BASE(DAT_OFFSET)
+#define S5P_GPIO_G1_PULL S5P_GPIO_G1_BASE(PULL_OFFSET)
+#define S5P_GPIO_G1_DRV S5P_GPIO_G1_BASE(DRV_OFFSET)
+#define S5P_GPIO_G1_PDNCON S5P_GPIO_G1_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_G1_PDNPUL S5P_GPIO_G1_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_G2_CON S5P_GPIO_G2_BASE(CON_OFFSET)
+#define S5P_GPIO_G2_DAT S5P_GPIO_G2_BASE(DAT_OFFSET)
+#define S5P_GPIO_G2_PULL S5P_GPIO_G2_BASE(PULL_OFFSET)
+#define S5P_GPIO_G2_DRV S5P_GPIO_G2_BASE(DRV_OFFSET)
+#define S5P_GPIO_G2_PDNCON S5P_GPIO_G2_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_G2_PDNPUL S5P_GPIO_G2_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_G3_CON S5P_GPIO_G3_BASE(CON_OFFSET)
+#define S5P_GPIO_G3_DAT S5P_GPIO_G3_BASE(DAT_OFFSET)
+#define S5P_GPIO_G3_PULL S5P_GPIO_G3_BASE(PULL_OFFSET)
+#define S5P_GPIO_G3_DRV S5P_GPIO_G3_BASE(DRV_OFFSET)
+#define S5P_GPIO_G3_PDNCON S5P_GPIO_G3_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_G3_PDNPUL S5P_GPIO_G3_BASE(PDNPULL_OFFSET)
+
+/* GPIO I Bank Base */
+#define S5P_GPIO_I_BASE(x) (S5P_GPIO_I_REG(0x0) + (x))
+
+#define S5P_GPIO_I_CON S5P_GPIO_I_BASE(CON_OFFSET)
+#define S5P_GPIO_I_DAT S5P_GPIO_I_BASE(DAT_OFFSET)
+#define S5P_GPIO_I_PULL S5P_GPIO_I_BASE(PULL_OFFSET)
+#define S5P_GPIO_I_DRV S5P_GPIO_I_BASE(DRV_OFFSET)
+#define S5P_GPIO_I_PDNCON S5P_GPIO_I_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_I_PDNPUL S5P_GPIO_I_BASE(PDNPULL_OFFSET)
+
+/* GPIO J Bank Base */
+#define S5P_GPIO_J0_BASE(x) (S5P_GPIO_J_REG(0x0) + (x))
+#define S5P_GPIO_J1_BASE(x) (S5P_GPIO_J_REG(0x20) + (x))
+#define S5P_GPIO_J2_BASE(x) (S5P_GPIO_J_REG(0x40) + (x))
+#define S5P_GPIO_J3_BASE(x) (S5P_GPIO_J_REG(0x60) + (x))
+#define S5P_GPIO_J4_BASE(x) (S5P_GPIO_J_REG(0x80) + (x))
+
+#define S5P_GPIO_J0_CON S5P_GPIO_J0_BASE(CON_OFFSET)
+#define S5P_GPIO_J0_DAT S5P_GPIO_J0_BASE(DAT_OFFSET)
+#define S5P_GPIO_J0_PULL S5P_GPIO_J0_BASE(PULL_OFFSET)
+#define S5P_GPIO_J0_DRV S5P_GPIO_J0_BASE(DRV_OFFSET)
+#define S5P_GPIO_J0_PDNCON S5P_GPIO_J0_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_J0_PDNPUL S5P_GPIO_J0_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_J1_CON S5P_GPIO_J1_BASE(CON_OFFSET)
+#define S5P_GPIO_J1_DAT S5P_GPIO_J1_BASE(DAT_OFFSET)
+#define S5P_GPIO_J1_PULL S5P_GPIO_J1_BASE(PULL_OFFSET)
+#define S5P_GPIO_J1_DRV S5P_GPIO_J1_BASE(DRV_OFFSET)
+#define S5P_GPIO_J1_PDNCON S5P_GPIO_J1_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_J1_PDNPUL S5P_GPIO_J1_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_J2_CON S5P_GPIO_J2_BASE(CON_OFFSET)
+#define S5P_GPIO_J2_DAT S5P_GPIO_J2_BASE(DAT_OFFSET)
+#define S5P_GPIO_J2_PULL S5P_GPIO_J2_BASE(PULL_OFFSET)
+#define S5P_GPIO_J2_DRV S5P_GPIO_J2_BASE(DRV_OFFSET)
+#define S5P_GPIO_J2_PDNCON S5P_GPIO_J2_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_J2_PDNPUL S5P_GPIO_J2_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_J3_CON S5P_GPIO_J3_BASE(CON_OFFSET)
+#define S5P_GPIO_J3_DAT S5P_GPIO_J3_BASE(DAT_OFFSET)
+#define S5P_GPIO_J3_PULL S5P_GPIO_J3_BASE(PULL_OFFSET)
+#define S5P_GPIO_J3_DRV S5P_GPIO_J3_BASE(DRV_OFFSET)
+#define S5P_GPIO_J3_PDNCON S5P_GPIO_J3_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_J3_PDNPUL S5P_GPIO_J3_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_J4_CON S5P_GPIO_J4_BASE(CON_OFFSET)
+#define S5P_GPIO_J4_DAT S5P_GPIO_J4_BASE(DAT_OFFSET)
+#define S5P_GPIO_J4_PULL S5P_GPIO_J4_BASE(PULL_OFFSET)
+#define S5P_GPIO_J4_DRV S5P_GPIO_J4_BASE(DRV_OFFSET)
+#define S5P_GPIO_J4_PDNCON S5P_GPIO_J4_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_J4_PDNPUL S5P_GPIO_J4_BASE(PDNPULL_OFFSET)
+
+/* GPIO K Bank Base */
+#define S5P_GPIO_K0_BASE(x) (S5P_GPIO_K_REG(0x0) + (x))
+#define S5P_GPIO_K1_BASE(x) (S5P_GPIO_K_REG(0x20) + (x))
+#define S5P_GPIO_K2_BASE(x) (S5P_GPIO_K_REG(0x40) + (x))
+#define S5P_GPIO_K3_BASE(x) (S5P_GPIO_K_REG(0x60) + (x))
+
+#define S5P_GPIO_K0_CON S5P_GPIO_K0_BASE(CON_OFFSET)
+#define S5P_GPIO_K0_DAT S5P_GPIO_K0_BASE(DAT_OFFSET)
+#define S5P_GPIO_K0_PULL S5P_GPIO_K0_BASE(PULL_OFFSET)
+#define S5P_GPIO_K0_DRV S5P_GPIO_K0_BASE(DRV_OFFSET)
+#define S5P_GPIO_K0_PDNCON S5P_GPIO_K0_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_K0_PDNPUL S5P_GPIO_K0_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_K1_CON S5P_GPIO_K1_BASE(CON_OFFSET)
+#define S5P_GPIO_K1_DAT S5P_GPIO_K1_BASE(DAT_OFFSET)
+#define S5P_GPIO_K1_PULL S5P_GPIO_K1_BASE(PULL_OFFSET)
+#define S5P_GPIO_K1_DRV S5P_GPIO_K1_BASE(DRV_OFFSET)
+#define S5P_GPIO_K1_PDNCON S5P_GPIO_K1_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_K1_PDNPUL S5P_GPIO_K1_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_K2_CON S5P_GPIO_K2_BASE(CON_OFFSET)
+#define S5P_GPIO_K2_DAT S5P_GPIO_K2_BASE(DAT_OFFSET)
+#define S5P_GPIO_K2_PULL S5P_GPIO_K2_BASE(PULL_OFFSET)
+#define S5P_GPIO_K2_DRV S5P_GPIO_K2_BASE(DRV_OFFSET)
+#define S5P_GPIO_K2_PDNCON S5P_GPIO_K2_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_K2_PDNPUL S5P_GPIO_K2_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_K3_CON S5P_GPIO_K3_BASE(CON_OFFSET)
+#define S5P_GPIO_K3_DAT S5P_GPIO_K3_BASE(DAT_OFFSET)
+#define S5P_GPIO_K3_PULL S5P_GPIO_K3_BASE(PULL_OFFSET)
+#define S5P_GPIO_K3_DRV S5P_GPIO_K3_BASE(DRV_OFFSET)
+#define S5P_GPIO_K3_PDNCON S5P_GPIO_K3_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_K3_PDNPUL S5P_GPIO_K3_BASE(PDNPULL_OFFSET)
+
+/* GPIO L Bank */
+#define S5P_GPIO_L0_BASE(x) (S5P_GPIO_L_REG(0x0) + (x))
+#define S5P_GPIO_L1_BASE(x) (S5P_GPIO_L_REG(0x20) + (x))
+#define S5P_GPIO_L2_BASE(x) (S5P_GPIO_L_REG(0x40) + (x))
+#define S5P_GPIO_L3_BASE(x) (S5P_GPIO_L_REG(0x60) + (x))
+#define S5P_GPIO_L4_BASE(x) (S5P_GPIO_L_REG(0x80) + (x))
+
+#define S5P_GPIO_L0_CON S5P_GPIO_L0_BASE(CON_OFFSET)
+#define S5P_GPIO_L0_DAT S5P_GPIO_L0_BASE(DAT_OFFSET)
+#define S5P_GPIO_L0_PULL S5P_GPIO_L0_BASE(PULL_OFFSET)
+#define S5P_GPIO_L0_DRV S5P_GPIO_L0_BASE(DRV_OFFSET)
+#define S5P_GPIO_L0_PDNCON S5P_GPIO_L0_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_L0_PDNPUL S5P_GPIO_L0_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_L1_CON S5P_GPIO_L1_BASE(CON_OFFSET)
+#define S5P_GPIO_L1_DAT S5P_GPIO_L1_BASE(DAT_OFFSET)
+#define S5P_GPIO_L1_PULL S5P_GPIO_L1_BASE(PULL_OFFSET)
+#define S5P_GPIO_L1_DRV S5P_GPIO_L1_BASE(DRV_OFFSET)
+#define S5P_GPIO_L1_PDNCON S5P_GPIO_L1_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_L1_PDNPUL S5P_GPIO_L1_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_L2_CON S5P_GPIO_L2_BASE(CON_OFFSET)
+#define S5P_GPIO_L2_DAT S5P_GPIO_L2_BASE(DAT_OFFSET)
+#define S5P_GPIO_L2_PULL S5P_GPIO_L2_BASE(PULL_OFFSET)
+#define S5P_GPIO_L2_DRV S5P_GPIO_L2_BASE(DRV_OFFSET)
+#define S5P_GPIO_L2_PDNCON S5P_GPIO_L2_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_L2_PDNPUL S5P_GPIO_L2_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_L3_CON S5P_GPIO_L3_BASE(CON_OFFSET)
+#define S5P_GPIO_L3_DAT S5P_GPIO_L3_BASE(DAT_OFFSET)
+#define S5P_GPIO_L3_PULL S5P_GPIO_L3_BASE(PULL_OFFSET)
+#define S5P_GPIO_L3_DRV S5P_GPIO_L3_BASE(DRV_OFFSET)
+#define S5P_GPIO_L3_PDNCON S5P_GPIO_L3_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_L3_PDNPUL S5P_GPIO_L3_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_L4_CON S5P_GPIO_L4_BASE(CON_OFFSET)
+#define S5P_GPIO_L4_DAT S5P_GPIO_L4_BASE(DAT_OFFSET)
+#define S5P_GPIO_L4_PULL S5P_GPIO_L4_BASE(PULL_OFFSET)
+#define S5P_GPIO_L4_DRV S5P_GPIO_L4_BASE(DRV_OFFSET)
+#define S5P_GPIO_L4_PDNCON S5P_GPIO_L4_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_L4_PDNPUL S5P_GPIO_L4_BASE(PDNPULL_OFFSET)
+
+/* GPIO MP Bank */
+#define S5P_MP_0_OFFSET 0x0
+#define S5P_MP_1_OFFSET 0x20
+#define S5P_MP_2_OFFSET 0x40
+#define S5P_MP_3_OFFSET 0x60
+#define S5P_MP_4_OFFSET 0x80
+#define S5P_MP_5_OFFSET 0xa0
+#define S5P_MP_6_OFFSET 0xc0
+#define S5P_MP_7_OFFSET 0xe0
+
+#define S5P_MP_0_BASE(x) (S5P_MP_REG(S5P_MP_0_OFFSET) + (x))
+#define S5P_MP_1_BASE(x) (S5P_MP_REG(S5P_MP_1_OFFSET) + (x))
+#define S5P_MP_2_BASE(x) (S5P_MP_REG(S5P_MP_2_OFFSET) + (x))
+#define S5P_MP_3_BASE(x) (S5P_MP_REG(S5P_MP_3_OFFSET) + (x))
+#define S5P_MP_4_BASE(x) (S5P_MP_REG(S5P_MP_4_OFFSET) + (x))
+#define S5P_MP_5_BASE(x) (S5P_MP_REG(S5P_MP_5_OFFSET) + (x))
+#define S5P_MP_6_BASE(x) (S5P_MP_REG(S5P_MP_6_OFFSET) + (x))
+#define S5P_MP_7_BASE(x) (S5P_MP_REG(S5P_MP_7_OFFSET) + (x))
+
+#define S5P_MP_0PULL S5P_MP_0_BASE(PULL_OFFSET)
+#define S5P_MP_0DRV S5P_MP_0_BASE(DRV_OFFSET)
+#define S5P_MP_0PDNPULL S5P_MP_0_BASE(PDNPULL_OFFSET)
+
+#define S5P_MP_1PULL S5P_MP_1_BASE(PULL_OFFSET)
+#define S5P_MP_1DRV S5P_MP_1_BASE(DRV_OFFSET)
+#define S5P_MP_1PDNPULL S5P_MP_1_BASE(PDNPULL_OFFSET)
+
+#define S5P_MP_2PULL S5P_MP_2_BASE(PULL_OFFSET)
+#define S5P_MP_2DRV S5P_MP_2_BASE(DRV_OFFSET)
+#define S5P_MP_2PDNPULL S5P_MP_2_BASE(PDNPULL_OFFSET)
+
+#define S5P_MP_3DRV S5P_MP_3_BASE(DRV_OFFSET)
+#define S5P_MP_4DRV S5P_MP_4_BASE(DRV_OFFSET)
+#define S5P_MP_5DRV S5P_MP_5_BASE(DRV_OFFSET)
+#define S5P_MP_6DRV S5P_MP_6_BASE(DRV_OFFSET)
+#define S5P_MP_7DRV S5P_MP_7_BASE(DRV_OFFSET)
+#define S5P_MP_8DRV S5P_MP_8_BASE(DRV_OFFSET)
+
+/* GPIO ETC Bank */
+#define S5P_ETC0_BASE(x) (S5P_ETC_REG(0x0) + (x))
+#define S5P_ETC1_BASE(x) (S5P_ETC_REG(0x20) + (x))
+#define S5P_ETC2_BASE(x) (S5P_ETC_REG(0x40) + (x))
+#define S5P_ETC3_BASE(x) (S5P_ETC_REG(0x60) + (x))
+#define S5P_ETC4_BASE(x) (S5P_ETC_REG(0x80) + (x))
+
+#define S5P_ETC0PULL S5P_ETC0_BASE(PULL_OFFSET)
+#define S5P_ETC0DRV S5P_ETC0_BASE(DRV_OFFSET)
+#define S5P_ETC1PULL S5P_ETC1_BASE(PULL_OFFSET)
+#define S5P_ETC1DRV S5P_ETC1_BASE(DRV_OFFSET)
+#define S5P_ETC2PULL S5P_ETC2_BASE(PULL_OFFSET)
+#define S5P_ETC2DRV S5P_ETC2_BASE(DRV_OFFSET)
+#define S5P_ETC3PULL S5P_ETC3_BASE(PULL_OFFSET)
+#define S5P_ETC3DRV S5P_ETC3_BASE(DRV_OFFSET)
+#define S5P_ETC4DRV S5P_ETC4_BASE(DRV_OFFSET)
+
+/* GPIO External Interrupt */
+#define S5P_GPIO_INT0_CON S5P_GPIO_INT_CON_REG(0x0)
+#define S5P_GPIO_INT1_CON S5P_GPIO_INT_CON_REG(0x4)
+#define S5P_GPIO_INT2_CON S5P_GPIO_INT_CON_REG(0x8)
+#define S5P_GPIO_INT3_CON S5P_GPIO_INT_CON_REG(0xc)
+#define S5P_GPIO_INT4_CON S5P_GPIO_INT_CON_REG(0x10)
+#define S5P_GPIO_INT5_CON S5P_GPIO_INT_CON_REG(0x14)
+#define S5P_GPIO_INT6_CON S5P_GPIO_INT_CON_REG(0x18)
+#define S5P_GPIO_INT7_CON S5P_GPIO_INT_CON_REG(0x1c)
+#define S5P_GPIO_INT8_CON S5P_GPIO_INT_CON_REG(0x20)
+#define S5P_GPIO_INT9_CON S5P_GPIO_INT_CON_REG(0x24)
+#define S5P_GPIO_INT10_CON S5P_GPIO_INT_CON_REG(0x28)
+#define S5P_GPIO_INT11_CON S5P_GPIO_INT_CON_REG(0x2c)
+#define S5P_GPIO_INT12_CON S5P_GPIO_INT_CON_REG(0x30)
+#define S5P_GPIO_INT13_CON S5P_GPIO_INT_CON_REG(0x34)
+#define S5P_GPIO_INT14_CON S5P_GPIO_INT_CON_REG(0x38)
+#define S5P_GPIO_INT15_CON S5P_GPIO_INT_CON_REG(0x3c)
+#define S5P_GPIO_INT16_CON S5P_GPIO_INT_CON_REG(0x40)
+#define S5P_GPIO_INT17_CON S5P_GPIO_INT_CON_REG(0x44)
+#define S5P_GPIO_INT18_CON S5P_GPIO_INT_CON_REG(0x48)
+#define S5P_GPIO_INT19_CON S5P_GPIO_INT_CON_REG(0x4c)
+#define S5P_GPIO_INT20_CON S5P_GPIO_INT_CON_REG(0x50)
+
+#define S5P_GPIO_INT0_FLTCON0 S5P_GPIO_INT_CON_REG(0x0)
+#define S5P_GPIO_INT0_FLTCON1 S5P_GPIO_INT_CON_REG(0x4)
+#define S5P_GPIO_INT1_FLTCON0 S5P_GPIO_INT_CON_REG(0x8)
+#define S5P_GPIO_INT1_FLTCON1 S5P_GPIO_INT_CON_REG(0xc)
+#define S5P_GPIO_INT2_FLTCON0 S5P_GPIO_INT_CON_REG(0x10)
+#define S5P_GPIO_INT2_FLTCON1 S5P_GPIO_INT_CON_REG(0x14)
+#define S5P_GPIO_INT3_FLTCON0 S5P_GPIO_INT_CON_REG(0x18)
+#define S5P_GPIO_INT3_FLTCON1 S5P_GPIO_INT_CON_REG(0x1c)
+#define S5P_GPIO_INT4_FLTCON0 S5P_GPIO_INT_CON_REG(0x20)
+#define S5P_GPIO_INT4_FLTCON1 S5P_GPIO_INT_CON_REG(0x24)
+#define S5P_GPIO_INT5_FLTCON0 S5P_GPIO_INT_CON_REG(0x28)
+#define S5P_GPIO_INT5_FLTCON1 S5P_GPIO_INT_CON_REG(0x2c)
+#define S5P_GPIO_INT6_FLTCON0 S5P_GPIO_INT_CON_REG(0x30)
+#define S5P_GPIO_INT6_FLTCON1 S5P_GPIO_INT_CON_REG(0x34)
+#define S5P_GPIO_INT7_FLTCON0 S5P_GPIO_INT_CON_REG(0x38)
+#define S5P_GPIO_INT7_FLTCON1 S5P_GPIO_INT_CON_REG(0x3c)
+#define S5P_GPIO_INT8_FLTCON0 S5P_GPIO_INT_CON_REG(0x40)
+#define S5P_GPIO_INT8_FLTCON1 S5P_GPIO_INT_CON_REG(0x44)
+#define S5P_GPIO_INT9_FLTCON0 S5P_GPIO_INT_CON_REG(0x48)
+#define S5P_GPIO_INT9_FLTCON1 S5P_GPIO_INT_CON_REG(0x4c)
+#define S5P_GPIO_INT10_FLTCON0 S5P_GPIO_INT_CON_REG(0x50)
+#define S5P_GPIO_INT11_FLTCON0 S5P_GPIO_INT_CON_REG(0x58)
+#define S5P_GPIO_INT11_FLTCON1 S5P_GPIO_INT_CON_REG(0x5c)
+#define S5P_GPIO_INT12_FLTCON0 S5P_GPIO_INT_CON_REG(0x60)
+#define S5P_GPIO_INT13_FLTCON0 S5P_GPIO_INT_CON_REG(0x68)
+#define S5P_GPIO_INT13_FLTCON1 S5P_GPIO_INT_CON_REG(0x6c)
+#define S5P_GPIO_INT14_FLTCON0 S5P_GPIO_INT_CON_REG(0x70)
+#define S5P_GPIO_INT14_FLTCON1 S5P_GPIO_INT_CON_REG(0x74)
+#define S5P_GPIO_INT15_FLTCON0 S5P_GPIO_INT_CON_REG(0x78)
+#define S5P_GPIO_INT15_FLTCON1 S5P_GPIO_INT_CON_REG(0x7c)
+#define S5P_GPIO_INT16_FLTCON0 S5P_GPIO_INT_CON_REG(0x80)
+#define S5P_GPIO_INT16_FLTCON1 S5P_GPIO_INT_CON_REG(0x84)
+#define S5P_GPIO_INT17_FLTCON0 S5P_GPIO_INT_CON_REG(0x88)
+#define S5P_GPIO_INT17_FLTCON1 S5P_GPIO_INT_CON_REG(0x8c)
+#define S5P_GPIO_INT18_FLTCON0 S5P_GPIO_INT_CON_REG(0x90)
+#define S5P_GPIO_INT18_FLTCON1 S5P_GPIO_INT_CON_REG(0x94)
+#define S5P_GPIO_INT19_FLTCON0 S5P_GPIO_INT_CON_REG(0x98)
+#define S5P_GPIO_INT19_FLTCON1 S5P_GPIO_INT_CON_REG(0x9c)
+#define S5P_GPIO_INT20_FLTCON0 S5P_GPIO_INT_CON_REG(0xa0)
+
+#define S5P_GPIO_INT0_MASK S5P_GPIO_INT_MASK_REG(0x00)
+#define S5P_GPIO_INT1_MASK S5P_GPIO_INT_MASK_REG(0x04)
+#define S5P_GPIO_INT2_MASK S5P_GPIO_INT_MASK_REG(0x08)
+#define S5P_GPIO_INT3_MASK S5P_GPIO_INT_MASK_REG(0x0c)
+#define S5P_GPIO_INT4_MASK S5P_GPIO_INT_MASK_REG(0x10)
+#define S5P_GPIO_INT5_MASK S5P_GPIO_INT_MASK_REG(0x14)
+#define S5P_GPIO_INT6_MASK S5P_GPIO_INT_MASK_REG(0x18)
+#define S5P_GPIO_INT7_MASK S5P_GPIO_INT_MASK_REG(0x1c)
+#define S5P_GPIO_INT8_MASK S5P_GPIO_INT_MASK_REG(0x20)
+#define S5P_GPIO_INT9_MASK S5P_GPIO_INT_MASK_REG(0x24)
+#define S5P_GPIO_INT10_MASK S5P_GPIO_INT_MASK_REG(0x28)
+#define S5P_GPIO_INT11_MASK S5P_GPIO_INT_MASK_REG(0x2c)
+#define S5P_GPIO_INT12_MASK S5P_GPIO_INT_MASK_REG(0x30)
+#define S5P_GPIO_INT13_MASK S5P_GPIO_INT_MASK_REG(0x34)
+#define S5P_GPIO_INT14_MASK S5P_GPIO_INT_MASK_REG(0x38)
+#define S5P_GPIO_INT15_MASK S5P_GPIO_INT_MASK_REG(0x3c)
+#define S5P_GPIO_INT16_MASK S5P_GPIO_INT_MASK_REG(0x40)
+#define S5P_GPIO_INT17_MASK S5P_GPIO_INT_MASK_REG(0x44)
+#define S5P_GPIO_INT18_MASK S5P_GPIO_INT_MASK_REG(0x48)
+#define S5P_GPIO_INT19_MASK S5P_GPIO_INT_MASK_REG(0x4c)
+#define S5P_GPIO_INT20_MASK S5P_GPIO_INT_MASK_REG(0x50)
+
+#define S5P_GPIO_INT0_PEND S5P_GPIO_INT_PEND_REG(0x00)
+#define S5P_GPIO_INT1_PEND S5P_GPIO_INT_PEND_REG(0x04)
+#define S5P_GPIO_INT2_PEND S5P_GPIO_INT_PEND_REG(0x08)
+#define S5P_GPIO_INT3_PEND S5P_GPIO_INT_PEND_REG(0x0c)
+#define S5P_GPIO_INT4_PEND S5P_GPIO_INT_PEND_REG(0x10)
+#define S5P_GPIO_INT5_PEND S5P_GPIO_INT_PEND_REG(0x14)
+#define S5P_GPIO_INT6_PEND S5P_GPIO_INT_PEND_REG(0x18)
+#define S5P_GPIO_INT7_PEND S5P_GPIO_INT_PEND_REG(0x1c)
+#define S5P_GPIO_INT8_PEND S5P_GPIO_INT_PEND_REG(0x20)
+#define S5P_GPIO_INT9_PEND S5P_GPIO_INT_PEND_REG(0x24)
+#define S5P_GPIO_INT10_PEND S5P_GPIO_INT_PEND_REG(0x28)
+#define S5P_GPIO_INT11_PEND S5P_GPIO_INT_PEND_REG(0x2c)
+#define S5P_GPIO_INT12_PEND S5P_GPIO_INT_PEND_REG(0x30)
+#define S5P_GPIO_INT13_PEND S5P_GPIO_INT_PEND_REG(0x34)
+#define S5P_GPIO_INT14_PEND S5P_GPIO_INT_PEND_REG(0x38)
+#define S5P_GPIO_INT15_PEND S5P_GPIO_INT_PEND_REG(0x3c)
+#define S5P_GPIO_INT16_PEND S5P_GPIO_INT_PEND_REG(0x40)
+#define S5P_GPIO_INT17_PEND S5P_GPIO_INT_PEND_REG(0x44)
+#define S5P_GPIO_INT18_PEND S5P_GPIO_INT_PEND_REG(0x48)
+#define S5P_GPIO_INT19_PEND S5P_GPIO_INT_PEND_REG(0x4c)
+#define S5P_GPIO_INT20_PEND S5P_GPIO_INT_PEND_REG(0x50)
+
+#define S5P_GPIO_INT_GRPPRI S5P_GPIO_INT_PRIO_REG(0x00)
+#define S5P_GPIO_INT_PRIORITY S5P_GPIO_INT_PRIO_REG(0x04)
+#define S5P_GPIO_INT_SERVICE S5P_GPIO_INT_PRIO_REG(0x08)
+#define S5P_GPIO_INT_SERVICE_PEND S5P_GPIO_INT_PRIO_REG(0x0c)
+#define S5P_GPIO_INT_GRPFIXPRI S5P_GPIO_INT_PRIO_REG(0x10)
+
+#define S5P_GPIO_INT0_FIXPRI S5P_GPIO_INT_PRIO_REG(0x14)
+#define S5P_GPIO_INT1_FIXPRI S5P_GPIO_INT_PRIO_REG(0x18)
+#define S5P_GPIO_INT2_FIXPRI S5P_GPIO_INT_PRIO_REG(0x1c)
+#define S5P_GPIO_INT3_FIXPRI S5P_GPIO_INT_PRIO_REG(0x20)
+#define S5P_GPIO_INT4_FIXPRI S5P_GPIO_INT_PRIO_REG(0x24)
+#define S5P_GPIO_INT5_FIXPRI S5P_GPIO_INT_PRIO_REG(0x28)
+#define S5P_GPIO_INT6_FIXPRI S5P_GPIO_INT_PRIO_REG(0x2c)
+#define S5P_GPIO_INT7_FIXPRI S5P_GPIO_INT_PRIO_REG(0x30)
+#define S5P_GPIO_INT8_FIXPRI S5P_GPIO_INT_PRIO_REG(0x34)
+#define S5P_GPIO_INT9_FIXPRI S5P_GPIO_INT_PRIO_REG(0x38)
+#define S5P_GPIO_INT10_FIXPRI S5P_GPIO_INT_PRIO_REG(0x3c)
+#define S5P_GPIO_INT11_FIXPRI S5P_GPIO_INT_PRIO_REG(0x40)
+#define S5P_GPIO_INT12_FIXPRI S5P_GPIO_INT_PRIO_REG(0x44)
+#define S5P_GPIO_INT13_FIXPRI S5P_GPIO_INT_PRIO_REG(0x48)
+#define S5P_GPIO_INT14_FIXPRI S5P_GPIO_INT_PRIO_REG(0x4c)
+#define S5P_GPIO_INT15_FIXPRI S5P_GPIO_INT_PRIO_REG(0x50)
+#define S5P_GPIO_INT16_FIXPRI S5P_GPIO_INT_PRIO_REG(0x54)
+#define S5P_GPIO_INT17_FIXPRI S5P_GPIO_INT_PRIO_REG(0x58)
+#define S5P_GPIO_INT18_FIXPRI S5P_GPIO_INT_PRIO_REG(0x5c)
+#define S5P_GPIO_INT19_FIXPRI S5P_GPIO_INT_PRIO_REG(0x60)
+#define S5P_GPIO_INT20_FIXPRI S5P_GPIO_INT_PRIO_REG(0x64)
+
+/* GPIO H Bank Base */
+#define S5P_GPIO_H0_BASE(x) (S5P_GPIO_H_REG(0x0) + (x))
+#define S5P_GPIO_H1_BASE(x) (S5P_GPIO_H_REG(0x20) + (x))
+#define S5P_GPIO_H2_BASE(x) (S5P_GPIO_H_REG(0x40) + (x))
+#define S5P_GPIO_H3_BASE(x) (S5P_GPIO_H_REG(0x60) + (x))
+
+#define S5P_GPIO_H0_CON S5P_GPIO_H0_BASE(CON_OFFSET)
+#define S5P_GPIO_H0_DAT S5P_GPIO_H0_BASE(DAT_OFFSET)
+#define S5P_GPIO_H0_PULL S5P_GPIO_H0_BASE(PULL_OFFSET)
+#define S5P_GPIO_H0_DRV S5P_GPIO_H0_BASE(DRV_OFFSET)
+#define S5P_GPIO_H0_PDNCON S5P_GPIO_H0_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_H0_PDNPUL S5P_GPIO_H0_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_H1_CON S5P_GPIO_H1_BASE(CON_OFFSET)
+#define S5P_GPIO_H1_DAT S5P_GPIO_H1_BASE(DAT_OFFSET)
+#define S5P_GPIO_H1_PULL S5P_GPIO_H1_BASE(PULL_OFFSET)
+#define S5P_GPIO_H1_DRV S5P_GPIO_H1_BASE(DRV_OFFSET)
+#define S5P_GPIO_H1_PDNCON S5P_GPIO_H1_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_H1_PDNPUL S5P_GPIO_H1_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_H2_CON S5P_GPIO_H2_BASE(CON_OFFSET)
+#define S5P_GPIO_H2_DAT S5P_GPIO_H2_BASE(DAT_OFFSET)
+#define S5P_GPIO_H2_PULL S5P_GPIO_H2_BASE(PULL_OFFSET)
+#define S5P_GPIO_H2_DRV S5P_GPIO_H2_BASE(DRV_OFFSET)
+#define S5P_GPIO_H2_PDNCON S5P_GPIO_H2_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_H2_PDNPUL S5P_GPIO_H2_BASE(PDNPULL_OFFSET)
+
+#define S5P_GPIO_H3_CON S5P_GPIO_H3_BASE(CON_OFFSET)
+#define S5P_GPIO_H3_DAT S5P_GPIO_H3_BASE(DAT_OFFSET)
+#define S5P_GPIO_H3_PULL S5P_GPIO_H3_BASE(PULL_OFFSET)
+#define S5P_GPIO_H3_DRV S5P_GPIO_H3_BASE(DRV_OFFSET)
+#define S5P_GPIO_H3_PDNCON S5P_GPIO_H3_BASE(PDNCON_OFFSET)
+#define S5P_GPIO_H3_PDNPUL S5P_GPIO_H3_BASE(PDNPULL_OFFSET)
+
+/* GPIO Wakeup Interrupt Configuration */
+#define S5P_GPIO_WAKEUP_INT0_CON S5P_WAKEUP_INT_CON(0x00)
+#define S5P_GPIO_WAKEUP_INT1_CON S5P_WAKEUP_INT_CON(0x04)
+#define S5P_GPIO_WAKEUP_INT2_CON S5P_WAKEUP_INT_CON(0x08)
+#define S5P_GPIO_WAKEUP_INT3_CON S5P_WAKEUP_INT_CON(0x0c)
+
+/* GPIO Wakeup Interrupt Filter Configuration */
+#define S5P_GPIO_WAKEUP_FLTINT0_CON0 S5P_WAKEUP_FLTINT_CON(0x00)
+#define S5P_GPIO_WAKEUP_FLTINT0_CON1 S5P_WAKEUP_FLTINT_CON(0x04)
+#define S5P_GPIO_WAKEUP_FLTINT1_CON0 S5P_WAKEUP_FLTINT_CON(0x08)
+#define S5P_GPIO_WAKEUP_FLTINT1_CON1 S5P_WAKEUP_FLTINT_CON(0x0c)
+#define S5P_GPIO_WAKEUP_FLTINT2_CON0 S5P_WAKEUP_FLTINT_CON(0x10)
+#define S5P_GPIO_WAKEUP_FLTINT2_CON1 S5P_WAKEUP_FLTINT_CON(0x14)
+#define S5P_GPIO_WAKEUP_FLTINT3_CON0 S5P_WAKEUP_FLTINT_CON(0x18)
+#define S5P_GPIO_WAKEUP_FLTINT3_CON1 S5P_WAKEUP_FLTINT_CON(0x1c)
+
+/* GPIO Wakeup Interrupt Mask */
+#define S5P_GPIO_WAKEUP_INT0_MASK S5P_WAKEUP_INT_MASK(0x00)
+#define S5P_GPIO_WAKEUP_INT1_MASK S5P_WAKEUP_INT_MASK(0x04)
+#define S5P_GPIO_WAKEUP_INT2_MASK S5P_WAKEUP_INT_MASK(0x08)
+#define S5P_GPIO_WAKEUP_INT3_MASK S5P_WAKEUP_INT_MASK(0x0c)
+
+/* GPIO Wakeup Interrupt Pend */
+#define S5P_GPIO_WAKEUP_INT0_PEND S5P_WAKEUP_INT_PEND(0x00)
+#define S5P_GPIO_WAKEUP_INT1_PEND S5P_WAKEUP_INT_PEND(0x04)
+#define S5P_GPIO_WAKEUP_INT2_PEND S5P_WAKEUP_INT_PEND(0x08)
+#define S5P_GPIO_WAKEUP_INT3_PEND S5P_WAKEUP_INT_PEND(0x0c)
+
diff --git a/include/asm-arm/arch-s5pc100/hardware.h
b/include/asm-arm/arch-s5pc100/hardware.h
new file mode 100644
index 0000000..84d24c9
--- /dev/null
+++ b/include/asm-arm/arch-s5pc100/hardware.h
@@ -0,0 +1,63 @@
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ARCH_HARDWARE_H_
+#define _ARCH_HARDWARE_H_
+
+#include <asm/sizes.h>
+
+#ifndef __ASSEMBLY__
+#define UData(Data) ((unsigned long) (Data))
+
+#define __REG(x) (*(vu_long *)(x))
+#define __REGl(x) (*(vu_long *)(x))
+#define __REGw(x) (*(vu_short *)(x))
+#define __REGb(x) (*(vu_char *)(x))
+#define __REG2(x, y) (*(vu_long *)((x) + (y)))
+#else
+#define UData(Data) (Data)
+
+#define __REG(x) (x)
+#define __REGl(x) (x)
+#define __REGw(x) (x)
+#define __REGb(x) (x)
+#define __REG2(x, y) ((x) + (y))
+#endif
+
+#define Fld(Size, Shft) (((Size) << 16) + (Shft))
+
+#define FSize(Field) ((Field) >> 16)
+#define FShft(Field) ((Field) & 0x0000FFFF)
+#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field) (UData (1) << FShft (Field))
+
+#define FClrBit(Data, Bit) (Data = (Data & ~(Bit)))
+#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field)))
+
+#define FInsrt(Value, Field) \
+ (UData (Value) << FShft (Field))
+
+#define FExtr(Data, Field) \
+ ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+#endif /* _ARCH_HARDWARE_H_ */
diff --git a/include/asm-arm/arch-s5pc100/map-base.h
b/include/asm-arm/arch-s5pc100/map-base.h
new file mode 100644
index 0000000..37cc9ba
--- /dev/null
+++ b/include/asm-arm/arch-s5pc100/map-base.h
@@ -0,0 +1,19 @@
+/* include/asm/arch/map-base.h
+ *
+ * Author: InKi Dae <inki.dae at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef ___ASM_ARCH_MAP_BASE_H
+#define ___ASM_ARCH_MAP_BASE_H
+
+#define S5P_ADDR_BASE 0xE1F00000
+
+#define S5P_ADDR(x) (S5P_ADDR_BASE + (x))
+
+#define S5P_LCD_BASE S5P_ADDR(0xC100000) /* Display Controller */
+
+#endif
diff --git a/include/asm-arm/arch-s5pc100/sys_proto.h
b/include/asm-arm/arch-s5pc100/sys_proto.h
new file mode 100644
index 0000000..b601547
--- /dev/null
+++ b/include/asm-arm/arch-s5pc100/sys_proto.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2009
+ * Samsung Electronics, <www.samsung.com/sec>
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2 at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+ulong get_PCLK(void);
+static inline s5pc1xx_uart_t *s5pc1xx_get_base_uart(enum s5pc1xx_uarts_nr nr);
+
+#endif
diff --git a/include/asm-arm/arch-s5pc100/uart.h
b/include/asm-arm/arch-s5pc100/uart.h
new file mode 100644
index 0000000..4d2482a
--- /dev/null
+++ b/include/asm-arm/arch-s5pc100/uart.h
@@ -0,0 +1,68 @@
+
+/*
+ * UART
+ */
+/* uart base address */
+#define S5P_PA_UART S5P_ADDR(0x0c000000) /* UART */
+#define UARTx_OFFSET(x) (S5P_PA_UART + x * 0x400)
+#define S5P_UART_BASE (S5P_PA_UART)
+/* uart offset */
+#define ULCON_OFFSET 0x00
+#define UCON_OFFSET 0x04
+#define UFCON_OFFSET 0x08
+#define UMCON_OFFSET 0x0C
+#define UTRSTAT_OFFSET 0x10
+#define UERSTAT_OFFSET 0x14
+#define UFSTAT_OFFSET 0x18
+#define UMSTAT_OFFSET 0x1C
+#define UTXH_OFFSET 0x20
+#define URXH_OFFSET 0x24
+#define UBRDIV_OFFSET 0x28
+#define UDIVSLOT_OFFSET 0x2C
+#define UINTP_OFFSET 0x30
+#define UINTSP_OFFSET 0x34
+#define UINTM_OFFSET 0x38
+
+#define UTRSTAT_TX_EMPTY (1 << 2)
+#define UTRSTAT_RX_READY (1 << 0)
+#define UART_ERR_MASK 0xF
+
+#ifndef __ASSEMBLY__
+typedef struct s5pc1xx_uart {
+ volatile unsigned long ULCON;
+ volatile unsigned long UCON;
+ volatile unsigned long UFCON;
+ volatile unsigned long UMCON;
+ volatile unsigned long UTRSTAT;
+ volatile unsigned long UERSTAT;
+ volatile unsigned long UFSTAT;
+ volatile unsigned long UMSTAT;
+#ifdef __BIG_ENDIAN
+ volatile unsigned char res1[3];
+ volatile unsigned char UTXH;
+ volatile unsigned char res2[3];
+ volatile unsigned char URXH;
+#else /* Little Endian */
+ volatile unsigned char UTXH;
+ volatile unsigned char res1[3];
+ volatile unsigned char URXH;
+ volatile unsigned char res2[3];
+#endif
+ volatile unsigned long UBRDIV;
+#ifdef __BIG_ENDIAN
+ volatile unsigned char res3[2];
+ volatile unsigned short UDIVSLOT;
+#else
+ volatile unsigned short UDIVSLOT;
+ volatile unsigned char res3[2];
+#endif
+} s5pc1xx_uart_t;
+
+enum s5pc1xx_uarts_nr {
+ S5PC1XX_UART0,
+ S5PC1XX_UART1,
+ S5PC1XX_UART2,
+ S5PC1XX_UART3,
+};
+#endif /* __ASSEMBLY__ */
+
diff --git a/include/asm-arm/arch-s5pc100/watchdog.h
b/include/asm-arm/arch-s5pc100/watchdog.h
new file mode 100644
index 0000000..668bb09
--- /dev/null
+++ b/include/asm-arm/arch-s5pc100/watchdog.h
@@ -0,0 +1,16 @@
+
+/*
+ * Watchdog
+ */
+#define S5P_WATCHDOG_BASE(x) (S5P_PA_WATCHDOG + (x))
+
+#define WTCON_OFFSET 0x0
+#define WTDAT_OFFSET 0x4
+#define WTCNT_OFFSET 0x8
+#define WTCLRINT_OFFSET 0xc
+
+#define S5P_WTCON S5P_WATCHDOG_BASE(WTCON_OFFSET)
+#define S5P_WTDAT S5P_WATCHDOG_BASE(WTDAT_OFFSET)
+#define S5P_WTCNT S5P_WATCHDOG_BASE(WTCNT_OFFSET)
+#define S5P_WTCLRINT S5P_WATCHDOG_BASE(WTCLRINT_OFFSET)
+
diff --git a/include/s5pc1xx-onenand.h b/include/s5pc1xx-onenand.h
new file mode 100644
index 0000000..5244536
--- /dev/null
+++ b/include/s5pc1xx-onenand.h
@@ -0,0 +1,105 @@
+#ifndef __S5PC1XX_ONENAND_H__
+#define __S5PC1XX_ONENAND_H__
+
+#include <asm/hardware.h>
+
+/*
+ * OneNAND Controller
+ */
+#define S5P_ONENAND_BASE 0xE7100000
+
+#define MEM_CFG_OFFSET 0x0000
+#define BURST_LEN_OFFSET 0x0010
+#define MEM_RESET_OFFSET 0x0020
+#define INT_ERR_STAT_OFFSET 0x0030
+#define INT_ERR_MASK_OFFSET 0x0040
+#define INT_ERR_ACK_OFFSET 0x0050
+#define ECC_ERR_STAT_OFFSET 0x0060
+#define ECC_ERR_STAT_1_OFFSET 0x0060
+#define MANUFACT_ID_OFFSET 0x0070
+#define DEVICE_ID_OFFSET 0x0080
+#define DATA_BUF_SIZE_OFFSET 0x0090
+#define BOOT_BUF_SIZE_OFFSET 0x00A0
+#define BUF_AMOUNT_OFFSET 0x00B0
+#define TECH_OFFSET 0x00C0
+#define FBA_WIDTH_OFFSET 0x00D0
+#define FPA_WIDTH_OFFSET 0x00E0
+#define FSA_WIDTH_OFFSET 0x00F0
+#define SYNC_MODE_OFFSET 0x0130
+#define TRANS_SPARE_OFFSET 0x0140
+#define ERR_PAGE_ADDR_OFFSET 0x0180
+#define INT_PIN_ENABLE_OFFSET 0x01A0
+#define ACC_CLOCK_OFFSET 0x01C0
+#define ERR_BLK_ADDR_OFFSET 0x01E0
+#define FLASH_VER_ID_OFFSET 0x01F0
+#define WATCHDOG_CNT_LOW_OFFSET 0x0260
+#define WATCHDOG_CNT_HI_OFFSET 0x0270
+#define SYNC_WRITE_OFFSET 0x0280
+#define COLD_RESET_DELAY_OFFSET 0x02A0
+#define DDP_DEVICE_OFFSET 0x02B0
+#define MULTI_PLANE_OFFSET 0x02C0
+#define TRANS_MODE_OFFSET 0x02E0
+#define ECC_ERR_STAT_2_OFFSET 0x0300
+#define ECC_ERR_STAT_3_OFFSET 0x0310
+#define ECC_ERR_STAT_4_OFFSET 0x0320
+#define DEV_PAGE_SIZE_OFFSET 0x0340
+#define INT_MON_STATUS_OFFSET 0x0390
+
+#define MEM_CFG0_REG __REG(S5P_ONENAND_BASE + MEM_CFG_OFFSET)
+#define BURST_LEN0_REG __REG(S5P_ONENAND_BASE + BURST_LEN_OFFSET)
+#define MEM_RESET0_REG __REG(S5P_ONENAND_BASE + MEM_RESET_OFFSET)
+#define INT_ERR_STAT0_REG __REG(S5P_ONENAND_BASE + INT_ERR_STAT_OFFSET)
+#define INT_ERR_MASK0_REG __REG(S5P_ONENAND_BASE + INT_ERR_MASK_OFFSET)
+#define INT_ERR_ACK0_REG __REG(S5P_ONENAND_BASE + INT_ERR_ACK_OFFSET)
+#define ECC_ERR_STAT0_REG __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_OFFSET)
+#define ECC_ERR_STAT_1_REG __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_1_OFFSET)
+#define MANUFACT_ID0_REG __REG(S5P_ONENAND_BASE + MANUFACT_ID_OFFSET)
+#define DEVICE_ID0_REG __REG(S5P_ONENAND_BASE + DEVICE_ID_OFFSET)
+#define DATA_BUF_SIZE0_REG __REG(S5P_ONENAND_BASE + DATA_BUF_SIZE_OFFSET)
+#define BOOT_BUF_SIZE0_REG __REG(S5P_ONENAND_BASE + BOOT_BUF_SIZE_OFFSET)
+#define FBA_WIDTH0_REG __REG(S5P_ONENAND_BASE + FBA_WIDTH_OFFSET)
+#define FPA_WIDTH0_REG __REG(S5P_ONENAND_BASE + FPA_WIDTH_OFFSET)
+#define FSA_WIDTH0_REG __REG(S5P_ONENAND_BASE + FSA_WIDTH_OFFSET)
+#define SYNC_MODE_REG __REG(S5P_ONENAND_BASE + SYNC_MODE_OFFSET)
+#define TRANS_SPARE0_REG __REG(S5P_ONENAND_BASE + TRANS_SPARE_OFFSET)
+#define ERR_PAGE_ADDR_REG __REG(S5P_ONENAND_BASE + ERR_PAGE_ADDR_OFFSET)
+#define DBS_DFS_WIDTH0_REG __REG(S5P_ONENAND_BASE + DBS_DFS_WIDTH_OFFSET)
+#define INT_PIN_ENABLE0_REG __REG(S5P_ONENAND_BASE + INT_PIN_ENABLE_OFFSET)
+#define ACC_CLOCK0_REG __REG(S5P_ONENAND_BASE + ACC_CLOCK_OFFSET)
+#define ERR_BLK_ADDR_REG __REG(S5P_ONENAND_BASE + ERR_BLK_ADDR_OFFSET)
+#define FLASH_VER_ID0_REG __REG(S5P_ONENAND_BASE + FLASH_VER_ID_OFFSET)
+#define WATCHDOG_CNT_LOW_REG __REG(S5P_ONENAND_BASE + WATCHDOG_CNT_LOW_OFFSET)
+#define WATCHDOG_CNT_HI_REG __REG(S5P_ONENAND_BASE + WATCHDOG_CNT_HI_OFFSET)
+#define SYNC_WRITE_REG __REG(S5P_ONENAND_BASE + SYNC_WRITE_OFFSET)
+#define COLD_RESET_DELAY_REG __REG(S5P_ONENAND_BASE + COLD_RESET_DELAY_OFFSET)
+#define TRANS_MODE_REG __REG(S5P_ONENAND_BASE + TRANS_MODE_OFFSET)
+#define DDP_DEVICE_REG __REG(S5P_ONENAND_BASE + DDP_DEVICE_OFFSET)
+#define MULTI_PLANE_REG __REG(S5P_ONENAND_BASE + MULTI_PLANE_OFFSET)
+#define ECC_ERR_STAT_2_REG __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_2_OFFSET)
+#define ECC_ERR_STAT_3_REG __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_3_OFFSET)
+#define ECC_ERR_STAT_4_REG __REG(S5P_ONENAND_BASE + ECC_ERR_STAT_4_OFFSET)
+#define DEV_PAGE_SIZE_REG __REG(S5P_ONENAND_BASE + DEV_PAGE_SIZE_OFFSET)
+#define INT_MON_STATUS_REG __REG(S5P_ONENAND_BASE + INT_MON_STATUS_OFFSET)
+
+#define ONENAND_MEM_RESET_HOT 0x3
+#define ONENAND_MEM_RESET_COLD 0x2
+#define ONENAND_MEM_RESET_WARM 0x1
+
+#define CACHE_OP_ERR (1 << 13)
+#define RST_CMP (1 << 12)
+#define RDY_ACT (1 << 11)
+#define INT_ACT (1 << 10)
+#define UNSUP_CMD (1 << 9)
+#define LOCKED_BLK (1 << 8)
+#define BLK_RW_CMP (1 << 7)
+#define ERS_CMP (1 << 6)
+#define PGM_CMP (1 << 5)
+#define LOAD_CMP (1 << 4)
+#define ERS_FAIL (1 << 3)
+#define PGM_FAIL (1 << 2)
+#define INT_TO (1 << 1)
+#define LD_FAIL_ECC_ERR (1 << 0)
+
+#define TSRF (1 << 0)
+
+#endif
--
1.5.6.3
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