[U-Boot] [PATCH 1/6] S5PC100: Samsung S5PC100 SoC support
Jean-Christophe PLAGNIOL-VILLARD
plagnioj at jcrosoft.com
Sun Jun 28 11:34:29 CEST 2009
On 17:05 Thu 25 Jun , HeungJun Kim wrote:
> S5PC100 processor is ARM Cortex A8 Processor SoC
> and SMDKC100 Board use this.
> So, this patch tested on SMDKC100 Board.
>
> I'll send 6 patch for working on SMDKC100 Board including this.
> But, this patch make the change to ARM Cortex A8 specific code
> like a cpu/arm_cortexa8/cpu.c, start.S.
>
> So, I wanna be reviewed to know how to contribute this whole patch.
this will go in a PATCH 0/X e-mail
please fix the commit message
>
> CC: Dirk Behme <dirk.behme at googlemail.com>
please @
> Signed-off-by: HeungJun, Kim <riverful.kim at samsung.com>
>
> ---
please rebase your patch as it's does not apply against the u-boot-arm master,
next or testing
>
> It includes the following :
>
> - Samsung S5PC100 SoC specific source codes
> - Samsung S5PC100 SoC specific header files
> - modify ARM Cortex A8 cpu.c, start.S
>
> cpu/arm_cortexa8/cpu.c | 80 +---
> cpu/arm_cortexa8/s5pc100/Makefile | 48 +++
> cpu/arm_cortexa8/s5pc100/config.mk | 36 ++
> cpu/arm_cortexa8/s5pc100/speed.c | 186 +++++++++
> cpu/arm_cortexa8/s5pc100/timer.c | 223 ++++++++++
> cpu/arm_cortexa8/start.S | 23 +
> include/asm-arm/arch-s5pc100/clock-others.h | 33 ++
> include/asm-arm/arch-s5pc100/cpu.h | 379 +++++++++++++++++
> include/asm-arm/arch-s5pc100/gpio.h | 580 +++++++++++++++++++++++++++
> include/asm-arm/arch-s5pc100/hardware.h | 63 +++
> include/asm-arm/arch-s5pc100/map-base.h | 19 +
> include/asm-arm/arch-s5pc100/sys_proto.h | 30 ++
> include/asm-arm/arch-s5pc100/uart.h | 68 ++++
> include/asm-arm/arch-s5pc100/watchdog.h | 16 +
> include/s5pc1xx-onenand.h | 105 +++++
> 15 files changed, 1828 insertions(+), 61 deletions(-)
> create mode 100644 cpu/arm_cortexa8/s5pc100/Makefile
> create mode 100644 cpu/arm_cortexa8/s5pc100/config.mk
> create mode 100644 cpu/arm_cortexa8/s5pc100/speed.c
> create mode 100644 cpu/arm_cortexa8/s5pc100/timer.c
> create mode 100644 include/asm-arm/arch-s5pc100/clock-others.h
> create mode 100644 include/asm-arm/arch-s5pc100/cpu.h
> create mode 100644 include/asm-arm/arch-s5pc100/gpio.h
> create mode 100644 include/asm-arm/arch-s5pc100/hardware.h
> create mode 100644 include/asm-arm/arch-s5pc100/map-base.h
> create mode 100644 include/asm-arm/arch-s5pc100/sys_proto.h
> create mode 100644 include/asm-arm/arch-s5pc100/uart.h
> create mode 100644 include/asm-arm/arch-s5pc100/watchdog.h
> create mode 100644 include/s5pc1xx-onenand.h
>
> diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
> index 6fd07d0..95e8523 100644
> --- a/cpu/arm_cortexa8/cpu.c
> +++ b/cpu/arm_cortexa8/cpu.c
> @@ -37,11 +37,28 @@
> #include <asm/system.h>
>
> #ifndef CONFIG_L2_OFF
> -void l2cache_disable(void);
> +void l2_cache_disable(void);
> +#endif
> +
> +#ifdef CONFIG_USE_IRQ
> +DECLARE_GLOBAL_DATA_PTR;
> #endif
>
> static void cache_flush(void);
>
> +int cpu_init(void)
> +{
> + /*
> + * setup up stacks if necessary
> + */
> +#ifdef CONFIG_USE_IRQ
> + IRQ_STACK_START =
> + _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
> + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
> +#endif
> + return 0;
> +}
no need please remove
> +
> int cleanup_before_linux(void)
> {
> unsigned int i;
> @@ -63,7 +80,7 @@ int cleanup_before_linux(void)
>
> #ifndef CONFIG_L2_OFF
> /* turn off L2 cache */
> - l2cache_disable();
> + l2_cache_disable();
> /* invalidate L2 cache also */
> v7_flush_dcache_all(get_device_type());
> #endif
> @@ -78,65 +95,6 @@ int cleanup_before_linux(void)
> return 0;
> }
>
<snip>
> diff --git a/cpu/arm_cortexa8/s5pc100/speed.c b/cpu/arm_cortexa8/s5pc100/speed.c
> new file mode 100644
> index 0000000..c5768f8
> --- /dev/null
> +++ b/cpu/arm_cortexa8/s5pc100/speed.c
> @@ -0,0 +1,186 @@
> +/*
> + * (C) Copyright 2009
> + * Inki Dae, SAMSUNG Electronics, <inki.dae at samsung.com>
> + * Heungjun Kim, SAMSUNG Electronics, <riverful.kim at samsung.com>
> + * Minkyu Kang, SAMSUNG Electronics, <mk7.kang at samsung.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * This code should work for both the S3C2400 and the S3C2410
> + * as they seem to have the same PLL and clock machinery inside.
> + * The different address mapping is handled by the s3c24xx.h files below.
> + */
> +
> +#include <common.h>
> +
> +#define APLL 0
> +#define MPLL 1
> +#define EPLL 2
> +#define HPLL 3
> +
> +/* ------------------------------------------------------------------------- */
> +/*
> + * NOTE: This describes the proper use of this file.
> + *
> + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
> + *
> + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
> + * the specified bus in HZ.
> + */
> +/* ------------------------------------------------------------------------- */
> +
> +static ulong get_PLLCLK(int pllreg)
please use this convention
get_xxx_clk_rate for all clock function
and please rename the file clock.c
and please create a clk.h file with this functions prototype
> +{
> + ulong r, m, p, s, mask;
> +
> + switch (pllreg) {
> + case APLL:
> + r = S5P_APLL_CON_REG;
> + break;
> + case MPLL:
> + r = S5P_MPLL_CON_REG;
> + break;
> + case EPLL:
> + r = S5P_EPLL_CON_REG;
> + break;
> + case HPLL:
> + r = S5P_HPLL_CON_REG;
> + break;
> + default:
> + hang();
> + }
> +
> + if (pllreg == APLL)
> + mask = 0x3ff;
> + else
> + mask = 0x0ff;
> +
> + m = (r >> 16) & mask;
> + p = (r >> 8) & 0x3f;
> + s = r & 0x7;
> +
> + return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
> +}
> +
> +/* return ARMCORE frequency */
<snip>
> +
> +#ifdef CONFIG_DISPLAY_CPUINFO
> +int print_cpuinfo(void)
> +{
> + unsigned int pid = __REG(S5P_PRO_ID);
> +
> + pid >>= 12;
> + pid &= 0x00fff;
> +
> + printf("CPU:\tS5PC%x@%luMHz\n", pid, get_ARMCLK() / 1000000);
> + printf("\tFclk = %luMHz, HclkD0 = %luMHz, PclkD0 = %luMHz,"
> + " PclkD1 = %luMHz\n",
> + get_FCLK() / 1000000, get_HCLK() / 1000000,
> + get_PCLKD0() / 1000000, get_PCLK() / 1000000);
> +
> + return 0;
> +}
> +#endif
please move this in cpu.c or cpu_info.c
> +
> diff --git a/cpu/arm_cortexa8/s5pc100/timer.c b/cpu/arm_cortexa8/s5pc100/timer.c
> new file mode 100644
> index 0000000..0864600
> --- /dev/null
> +++ b/cpu/arm_cortexa8/s5pc100/timer.c
> @@ -0,0 +1,223 @@
> +/*
> + * (C) Copyright 2003
> + * Texas Instruments <www.ti.com>
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger at sysgo.de>
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Alex Zuepke <azu at sysgo.de>
> + *
> + * (C) Copyright 2002-2004
> + * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
> + *
> + * (C) Copyright 2004
> + * Philippe Robin, ARM Ltd. <philippe.robin at arm.com>
> + *
> + * (C) Copyright 2008
> + * Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
all there people write the code?
> + *
> + * (C) Copyright 2009
> + * Heungjun Kim, SAMSUNG Electronics, <riverful.kim at samsung.com>
> + * Inki Dae, SAMSUNG Electronics, <inki.dae at samsung.com>
> + * Minkyu Kang, SAMSUNG Electronics, <mk7.kang at samsung.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +
> +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
> +#define MUX_DIV_2 (1) /* 1/2 period */
> +#define MUX_DIV_4 (2) /* 1/4 period */
> +#define MUX_DIV_8 (3) /* 1/8 period */
> +#define MUX_DIV_16 (4) /* 1/16 period */
> +#define MUX4_DIV_SHIFT 16
> +
> +#define TCON_TIMER4_SHIFT 20
> +
> +static ulong count_value;
> +
> +/* Internal tick units */
> +static unsigned long long timestamp; /* Monotonic incrementing timer */
> +static unsigned long lastdec; /* Last decremneter snapshot */
> +
> +/* macro to read the 16 bit timer */
> +static inline ulong READ_TIMER(void)
> +{
> + const s5pc1xx_timers_t *timers = (s5pc1xx_timers_t *) S5P_TIMER_BASE;
> +
> + return timers->TCNTO4;
> +}
> +
> +int timer_init(void)
> +{
> + s5pc1xx_timers_t *timers = (s5pc1xx_timers_t *) S5P_TIMER_BASE;
> +
> + /*
> + * @ PWM Timer 4
> + * Timer Freq(HZ) =
> + * PCLK / { (prescaler_value + 1) * (divider_value) }
> + */
> +
> + /* set prescaler : 16 */
> + /* set divider : 2 */
> + timers->TCFG0 = (PRESCALER_1 & 0xff) << 8;
> + timers->TCFG1 = (MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT;
> +
> + if (count_value == 0) {
> +
> + /* reset initial value */
> + /* count_value = 2085937.5(HZ) (per 1 sec)*/
> + count_value = get_PCLK() / ((PRESCALER_1 + 1) *
> + (MUX_DIV_2 + 1));
> +
> + /* count_value / 100 = 20859.375(HZ) (per 10 msec) */
> + count_value = count_value / 100;
> + }
> +
> + /* set count value */
> + timers->TCNTB4 = count_value;
> + lastdec = count_value;
> +
> + /* auto reload & manual update */
> + timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) |
> + S5P_TCON4_AUTO_RELOAD | S5P_TCON4_UPDATE;
> +
> + /* start PWM timer 4 */
> + timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) |
> + S5P_TCON4_AUTO_RELOAD | S5P_TCON4_ON;
> +
> + timestamp = 0;
> +
> + return 0;
> +}
> +
please remove one empty file
> +
> +/*
> + * timer without interrupts
> + */
<snip>
> +
> +void reset_cpu(ulong ignored)
please move this to reset.c or cpu.c
it's not related to the timer
> +{
> + unsigned int pid = __REG(S5P_PRO_ID);
> +
> + pid >>= 12;
> + pid &= 0x00fff;
> + pid |= (0xC << 12);
> +
> + __REG(S5P_SW_RST) = pid;
> +
> + while (1) ;
> +}
> diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S
> index 66b4820..da6eed7 100644
> --- a/cpu/arm_cortexa8/start.S
> +++ b/cpu/arm_cortexa8/start.S
> @@ -34,6 +34,7 @@
>
> .globl _start
> _start: b reset
> +#ifndef CONFIG_ONENAND_IPL
please sync with arm1136/start.S
I do want to have multiple start.S implementation anymore
please also note the we introduce a CONFIG_PRELOADER
> ldr pc, _undefined_instruction
> ldr pc, _software_interrupt
> ldr pc, _prefetch_abort
> @@ -50,6 +51,9 @@ _not_used: .word not_used
> _irq: .word irq
> _fiq: .word fiq
> _pad: .word 0x12345678 /* now 16*4=64 */
> +#else
> + . = _start + 64
> +#endif
> .global _end_vect
> _end_vect:
>
> @@ -108,6 +112,7 @@ reset:
> orr r0, r0, #0xd3
> msr cpsr,r0
>
> +#ifndef CONFIG_ONENAND_IPL
> #if (CONFIG_OMAP34XX)
> /* Copy vectors to mask ROM indirect addr */
> adr r0, _start @ r0 <- current position of code
> @@ -131,11 +136,13 @@ next:
> bl cpy_clk_code @ put dpll adjust code behind vectors
> #endif /* NAND Boot */
> #endif
> +#endif /* CONFIG_ONENAND_IPL */
> /* the mask ROM code should have PLL and others stable */
> #ifndef CONFIG_SKIP_LOWLEVEL_INIT
> bl cpu_init_crit
> #endif
>
<snip>
> /*
> *************************************************************************
> *
> @@ -502,6 +522,7 @@ finished_inval:
> ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
>
>
> +#if (CONFIG_OMAP34XX)
> .align 5
> .global reset_cpu
> reset_cpu:
> @@ -514,3 +535,5 @@ _loop_forever:
> b _loop_forever
> rstctl:
> .word PRM_RSTCTRL
> +#endif
please move this reset_cpu to cortexA8/omap3/
> +#endif /* CONFIG_ONENAND_IPL */
> diff --git a/include/asm-arm/arch-s5pc100/clock-others.h
> b/include/asm-arm/arch-s5pc100/clock-others.h
> new file mode 100644
> index 0000000..35f1686
> --- /dev/null
> +++ b/include/asm-arm/arch-s5pc100/clock-others.h
> @@ -0,0 +1,33 @@
please add licence header
> +
> +/*
> + * Clock control - Others
> + */
<snip>
> +
> diff --git a/include/asm-arm/arch-s5pc100/cpu.h
> b/include/asm-arm/arch-s5pc100/cpu.h
> new file mode 100644
> index 0000000..6ec8656
> --- /dev/null
> +++ b/include/asm-arm/arch-s5pc100/cpu.h
> @@ -0,0 +1,379 @@
> +/*
> + * (C) Copyright 2009
> + * Samsung Electronics, <www.samsung.com/sec>
> + * Heungjun Kim <riverful.kim at samsung.com>
> + * Minkyu Kang <mk7.kang at samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef _CPU_H
> +#define _CPU_H
> +
please split this file a few more as somethink like this
clock.h
pwm.h
power.h etc....
please also not that you have whitespace and your patch is line wrapped
> +#include <asm/hardware.h>
> +
> +#ifndef __S5PC100_H__
> +#define __S5PC100_H__
> +
> +#define S5P_ADDR_BASE 0xe0000000
> +#define S5P_ADDR(x) (S5P_ADDR_BASE + (x))
> +
> +#define S5P_PA_ID S5P_ADDR(0x00000000) /* Chip ID Base */
> +#define S5P_PA_CLK S5P_ADDR(0x00100000) /* Clock Base */
> +#define S5P_PA_PWR S5P_ADDR(0x00108000) /* Power Base */
> +#define S5P_PA_CLK_OTHERS S5P_ADDR(0x00200000) /* Clock Others Base */
> +#define S5P_PA_GPIO S5P_ADDR(0x00300000) /* GPIO Base */
> +#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Vector Interrupt
> Controller 0 */
> +#define S5P_PA_VIC1 S5P_ADDR(0x04100000) /* Vector Interrupt
> Controller 1 */
> +#define S5P_PA_VIC2 S5P_ADDR(0x04200000) /* Vector Interrupt
> Controller 2 */
> +#define S5P_PA_DMC S5P_ADDR(0x06000000) /* Dram Memory Controller */
> +#define S5P_PA_SROMC S5P_ADDR(0x07000000) /* SROM Controller */
> +#define S5P_PA_WATCHDOG S5P_ADDR(0x0a200000) /* Watchdog Timer */
> +#define S5P_PA_PWMTIMER S5P_ADDR(0x0a000000) /* PWM Timer */
> +
> +/*
> + * Chip ID
> + */
> +#define S5P_ID(x) (S5P_PA_ID + (x))
> +
> +#define S5P_PRO_ID S5P_ID(0)
> +#define S5P_OMR S5P_ID(4)
> +
<snip>
> +
> +#include <asm/arch/uart.h>
> +#include <asm/arch/watchdog.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/clock-others.h>
why do you include it?
> +
> +#endif /* __S5PC100_H__ */
> +
> +#endif /* _CPU_H */
<snip>
> diff --git a/include/asm-arm/arch-s5pc100/hardware.h
> b/include/asm-arm/arch-s5pc100/hardware.h
> new file mode 100644
> index 0000000..84d24c9
> --- /dev/null
> +++ b/include/asm-arm/arch-s5pc100/hardware.h
> @@ -0,0 +1,63 @@
> +/*
> + * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
> + *
> + * (C) Copyright 2008
> + * Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _ARCH_HARDWARE_H_
> +#define _ARCH_HARDWARE_H_
> +
> +#include <asm/sizes.h>
> +
> +#ifndef __ASSEMBLY__
> +#define UData(Data) ((unsigned long) (Data))
> +
> +#define __REG(x) (*(vu_long *)(x))
> +#define __REGl(x) (*(vu_long *)(x))
> +#define __REGw(x) (*(vu_short *)(x))
> +#define __REGb(x) (*(vu_char *)(x))
> +#define __REG2(x, y) (*(vu_long *)((x) + (y)))
> +#else
> +#define UData(Data) (Data)
> +
> +#define __REG(x) (x)
> +#define __REGl(x) (x)
> +#define __REGw(x) (x)
> +#define __REGb(x) (x)
> +#define __REG2(x, y) ((x) + (y))
> +#endif
please use proper accessor in the file, so you do not need those macro
> +
> +#define Fld(Size, Shft) (((Size) << 16) + (Shft))
> +
> +#define FSize(Field) ((Field) >> 16)
> +#define FShft(Field) ((Field) & 0x0000FFFF)
> +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
> +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
> +#define F1stBit(Field) (UData (1) << FShft (Field))
> +
> +#define FClrBit(Data, Bit) (Data = (Data & ~(Bit)))
> +#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field)))
> +
> +#define FInsrt(Value, Field) \
> + (UData (Value) << FShft (Field))
> +
> +#define FExtr(Data, Field) \
> + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
please use generic bits ops
> +
> +#endif /* _ARCH_HARDWARE_H_ */
Best Regards,
J.
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