[U-Boot] Uboot and ARM SMP support

[Shilimkar, Santosh]

> -----Original Message-----
> From: Dirk Behme [mailto:dirk.behme at googlemail.com] 
> Sent: Thursday, June 25, 2009 9:19 PM
> To: Shilimkar, Santosh
> Cc: Pandita, Vikram; Jean-Christophe PLAGNIOL-VILLARD; 
> Nishanth Menon; u-boot at lists.denx.de; Tom; Peter Pearse
> Subject: Re: [U-Boot] Uboot and ARM SMP support
> 
> Shilimkar, Santosh wrote:
> >> -----Original Message-----
> >> From: Pandita, Vikram 
> >> Sent: Thursday, June 25, 2009 6:32 PM
> >> To: Jean-Christophe PLAGNIOL-VILLARD; Nishanth Menon; 
> >> Shilimkar, Santosh
> >> Cc: Sudeep K N; u-boot at lists.denx.de; Tom
> >> Subject: RE: [U-Boot] Uboot and ARM SMP support
> >>
> >> Adding Santosh to loop who has pushed the OMAP4 SMP support 
> >> into Kernel.org
> >>
> >>
> >>> -----Original Message-----
> >>> From: Jean-Christophe PLAGNIOL-VILLARD 
> [mailto:plagnioj at jcrosoft.com]
> >>> Sent: Thursday, June 25, 2009 7:44 AM
> >>> To: Nishanth Menon
> >>> Cc: Sudeep K N; u-boot at lists.denx.de; Pandita, Vikram; Tom
> >>> Subject: Re: [U-Boot] Uboot and ARM SMP support
> >>>
> >>> On 12:47 Thu 25 Jun     , Nishanth Menon wrote:
> >>>> Sudeep K N said the following on 06/25/2009 12:11 PM:
> >>>>> Sorry, may be I confused you.
> >>>>> I indent to use only one core for u-boot.
> >>>>> I wanted to ask whether we need to update the cache
> >>>>> management to boot for ARM Cortex A9 SMP if we take
> >>>>> ARM Cortex A8 code as base.
> >>>>> I have tried and did not require any change on top of A8 code
> >>>>> to run u-boot on A9 SMP.
> >>>>> Is that right approach?
> >>>>>
> >>>>>
> >>>> you may want to see [1] how this was done for OMAP4 (which 
> >> has a SMP
> >>>> cortex A9)-> we can discuss how to setup cortex_a9 in 
> >> mainline u-boot.
> >>>> My thought would be: cpu/arm_cortexa9 - considering that 
> >> a9 cores could
> >>>> be from 1 to 4 or so if my memory serves right -> btw, I 
> >> wonder how SMP
> >>>> handling is done in u-boot today..
> >>> for arm I've only a theorical design as I've no SMP board for now
> >>> but I want to see SMP boot & AMP boot supported in Mainline
> >>>
> > 
> > The approach is perfect and that's what is most of the SMP 
> systems are doing..
> > If one look at the linux framework, U-boot need not know 
> about the secondary cores.
> > 
> > As far as caches goes, the SCU is not enabled at u-boot 
> level so there is no coherency
> > between L1 caches.L2 is external and not enabled at u-boot 
> level for time being.
> > At the point when u-boot transfer control to kernel, the 
> caches are flushed in the 
> > clean-up path so you need not do any explicit stuff.
> > 
> > In case you want to enable L2 cache ( if preset ), then you 
> need to add support for 
> > that in the u-boot. 
> > 
> > So essentially u-boot would be almost same as Cortex-A8 
> except you should avoid programming AuxControl
> > register because the bit definitions are different.
> 
> Yes.
> 
> What I think what I (hopefully correctly) understood looking at 
> Peter's (looping him in, btw) U-Boot branch
> 
> http://www.linux-arm.org/git?p=u-boot-armdev.git;a=summary
> 
> is:
> 
> * Regarding U-Boot (ARM) SMP support:
> 
> There isn't any need for U-Boot (cpu directory) to deal with it. 
> Concept seems to be "handle ARM11 MPcore as ARM11 single core and 
> Cortex A9 SMP as Cortex A8" at U-Boot level. I.e. boot only 
> the master 
> processor and cover it with existing single processor code in cpu 
> directory. Then use board specific low_levelinit.S to put other 
> (slave) processors into WFI mode. That's all.
This perfectly summarises that we don't need to have A9 specific
Directory. Regarding doing something on secondary core, it can be handled
In boot monitor(ROM code) or as suggested in u-boot itself.

> * Regarding cpu/cortex_a9 directory:
> 
> No need for it. I don't know A9, but looking e.g. at
> 
> http://www.linux-arm.org/git?p=u-boot-armdev.git;a=blobdiff;f=
> MAKEALL;h=84f4bf8862cd49f109174de62777e4bd3499ab03;hp=67030a73
55d56d751fdc4499e3c82d8fdb615d6e;hb=eb72ea08d09b7e7ac96d7dc3f428a63f53d266e1;hpb=> 2e6979454a2ea76c6b2889e40cde2e0ee9ad5e50
> http://www.linux-arm.org/git?p=u-boot-armdev.git;a=blobdiff;f=
> MAKEALL;h=67030a7355d56d751fdc4499e3c82d8fdb615d6e;hp=72cc4ee0
d90b5feb90ffe1fc48ddb6c3a0850907;hb=> 2e6979454a2ea76c6b2889e40cde2e0ee9ad5e50;hpb=ecad37d06857bb4f5
> 7bb95e0e0246a68b4d58161
> 
> and above idea of re-using single processor core cpu/arm* code, I 
> would propose to rename cpu/cortex_a8 to cpu/cortex_ax. And cover A9 
> with this, too.
This looks good to me. We just need to handle AuxControl reg bits and L2 cache
Bit differntly for A9.
> As I don't have an A9 nor know the details, I'm not sure if 
> this would 
> work in real life, but the basic idea sounds good for.
> 
> Maybe Peter can share his ideas or experience?
Regards,
Santosh