[U-Boot] [PATCH 4/4 v2] arm nomadik: use 1000 as HZ value and rewrite timer code

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:19 Mon 22 Jun     , Alessandro Rubini wrote:
> From: Alessandro Rubini <rubini at unipv.it>
> 
> This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites
> timer code, which is now both correct and much smaller.  Unused
> functions like udelay_masked() have been removed as no driver uses
> them, even the ones that are not currently active for this board.
> 
> Signed-off-by: Alessandro Rubini <rubini at unipv.it>
> Acked-by: Andrea Gallo <andrea.gallo at stericsson.com>
for the record what is its precision now?
> ---
>  cpu/arm926ejs/nomadik/timer.c |  190 +++++++++++-----------------------------
>  include/configs/nhk8815.h     |    2 +-
>  2 files changed, 53 insertions(+), 139 deletions(-)
> 
> diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c
> index 2870d24..3618c4a 100644
> --- a/cpu/arm926ejs/nomadik/timer.c
> +++ b/cpu/arm926ejs/nomadik/timer.c
> @@ -1,20 +1,5 @@
>  /*
> - * (C) Copyright 2003
> - * Texas Instruments <www.ti.com>
> - *
> - * (C) Copyright 2002
> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> - * Marius Groeger <mgroeger at sysgo.de>
> - *
> - * (C) Copyright 2002
> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> - * Alex Zuepke <azu at sysgo.de>
> - *
> - * (C) Copyright 2002-2004
> - * Gary Jennejohn, DENX Software Engineering, <garyj at denx.de>
> - *
> - * (C) Copyright 2004
> - * Philippe Robin, ARM Ltd. <philippe.robin at arm.com>
> + * (C) Copyright 2009 Alessandro Rubini
>   *
>   * See file CREDITS for list of people who contributed to this
>   * project.
> @@ -38,145 +23,74 @@
>  #include <common.h>
>  #include <asm/io.h>
>  
> -#define TIMER_LOAD_VAL 0xffffffff
> +/*
> + * Registers in the MTU block -- same as <mach/mtu.h> in linux 
so please simply import it
> +*/
> +
> +#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
> +#define MTU_RIS		0x04	/* Raw interrupt status */
> +#define MTU_MIS		0x08	/* Masked interrupt status */
> +#define MTU_ICR		0x0C	/* Interrupt clear register */
> +
> +/* per-timer registers take 0..3 as argument */
> +#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
> +#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
> +#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
> +#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */
> +
> +/* bits for the control register */
> +#define MTU_CRn_ENA		0x80
> +#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
> +#define MTU_CRn_PRESCALE_MASK	0x0c
> +#define MTU_CRn_PRESCALE_1		0x00
> +#define MTU_CRn_PRESCALE_16		0x04
> +#define MTU_CRn_PRESCALE_256		0x08
> +#define MTU_CRn_32BITS		0x02
> +#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/
>  
> -/* macro to read the 32 bit timer */
> -#define READ_TIMER readl(CONFIG_SYS_TIMERBASE + 20)
>  
> -static ulong timestamp;
> -static ulong lastdec;
> +/*
> + * The timer is a decrementer, we'll left it free running at 2.4MHz.
> + * We have 2.4 ticks per microsecond and an overflow in almost 30min
> + */
> +#define TIMER_CLOCK		(24*100*1000)
> +#define COUNT_TO_USEC(x)	((x)*5/12) /* overflows at 6min */
please add space before and after */
> +#define USEC_TO_COUNT(x)	((x)*12/5) /* overflows at 6min */
> +#define TICKS_PER_HZ		(TIMER_CLOCK/CONFIG_SYS_HZ)
> +#define TICKS_TO_HZ(x)		((x)/TICKS_PER_HZ)
> +
> +/* macro to read the 32 bit timer: since it decrements, we invert read value */
> +#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
>  
> -/* nothing really to do with interrupts, just starts up a counter. */
> +/* Configure a free-running, auto-wrap counter with no prescaler */
>  int timer_init(void)
>  {
> -	/* Load timer with initial value */
> -	writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + 16);
> -
> -	/*
> -	 * Set timer to be enabled, free-running, no interrupts, 256 divider,
> -	 * 32-bit, wrap-mode
> -	 */
> -	writel(0x8a, CONFIG_SYS_TIMERBASE + 24);
> -
> -	/* init the timestamp and lastdec value */
> -	reset_timer_masked();
> -
> +	writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
> +	       CONFIG_SYS_TIMERBASE + MTU_CR(0));
> +	reset_timer();
>  	return 0;
>  }
>  
> -/*
> - * timer without interrupts
> - */
> +/* Restart counting from 0 */
>  void reset_timer(void)
>  {
> -	reset_timer_masked();
> +	writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */
>  }
>  
> +/* Return how many HZ passed since "base" */
>  ulong get_timer(ulong base)
>  {
> -	return get_timer_masked() - base;
> -}
> -
> -void set_timer(ulong t)
> -{
> -	timestamp = t;
> +	ulong res = TICKS_TO_HZ(READ_TIMER()) - base;
please return directly
> +	return res;
>  }
>  
Best Regards,
J.