[U-Boot] [RFC PATCH] Add support for Raidsonic ICYBOX NAS4220 board
Darius Augulis
augulis.darius at gmail.com
Tue Jun 30 21:03:47 CEST 2009
This board is based on Cortina Systems networking processor
CS3516. It has FA526 core, which is ARMv4 compatible.
Many SoC specific definitions may be used for similar
processors CS3512 and dual-core CS3518. This processor
family has Gemini name.
Signed-off-by: Darius Augulis <augulis.darius at gmail.com>
---
MAINTAINERS | 4 +
MAKEALL | 1
Makefile | 3
board/nas4220/Makefile | 43 +++++
board/nas4220/config.mk | 14 ++
board/nas4220/lowlevel_init.S | 96 ++++++++++++
board/nas4220/nas4220.c | 75 +++++++++
board/nas4220/u-boot.lds | 48 ++++++
cpu/arm920t/gemini/Makefile | 38 +++++
cpu/arm920t/gemini/timer.c | 93 ++++++++++++
cpu/arm920t/start.S | 11 +
include/asm-arm/arch-gemini/gemini.h | 271 ++++++++++++++++++++++++++++++++++
include/configs/nas4220.h | 116 +++++++++++++++
13 files changed, 811 insertions(+), 2 deletions(-)
create mode 100644 board/nas4220/Makefile
create mode 100644 board/nas4220/config.mk
create mode 100644 board/nas4220/lowlevel_init.S
create mode 100644 board/nas4220/nas4220.c
create mode 100644 board/nas4220/u-boot.lds
create mode 100644 cpu/arm920t/gemini/Makefile
create mode 100644 cpu/arm920t/gemini/timer.c
create mode 100644 include/asm-arm/arch-gemini/gemini.h
create mode 100644 include/configs/nas4220.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9379c7e..ade43ed 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -671,6 +671,10 @@ Sergey Lapin <slapin at ossfans.org>
afeb9260 ARM926EJS (AT91SAM9260 SoC)
+Darius Augulis <augulis.darius at gmail.com>
+
+ nas4220 CS3516
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/MAKEALL b/MAKEALL
index f4599d6..8d28e36 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -511,6 +511,7 @@ LIST_ARM9=" \
lpd7a400 \
mx1ads \
mx1fs2 \
+ nas4220 \
netstar \
nmdk8815 \
omap1510inn \
diff --git a/Makefile b/Makefile
index bcc81c9..99c59c3 100644
--- a/Makefile
+++ b/Makefile
@@ -2836,6 +2836,9 @@ mx1ads_config : unconfig
mx1fs2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
+nas4220_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t nas4220 NULL gemini
+
netstar_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm925t netstar
diff --git a/board/nas4220/Makefile b/board/nas4220/Makefile
new file mode 100644
index 0000000..8299ffd
--- /dev/null
+++ b/board/nas4220/Makefile
@@ -0,0 +1,43 @@
+#
+# (c) Copyright 2009
+# Linkodas, Inc.
+# http://www.linkodas.com
+#
+# Darius Augulis <daugulis at linkodas.com> <augulis.darius at gmail.com>
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := nas4220.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nas4220/config.mk b/board/nas4220/config.mk
new file mode 100644
index 0000000..5b418ba
--- /dev/null
+++ b/board/nas4220/config.mk
@@ -0,0 +1,14 @@
+#
+# (c) Copyright 2009
+# Linkodas, Inc.
+# http://www.linkodas.com
+#
+# Author: Darius Augulis <daugulis at linkodas.com> <augulis.darius at gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+
+TEXT_BASE = 0x10400000
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
diff --git a/board/nas4220/lowlevel_init.S b/board/nas4220/lowlevel_init.S
new file mode 100644
index 0000000..d51a5a2
--- /dev/null
+++ b/board/nas4220/lowlevel_init.S
@@ -0,0 +1,96 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <daugulis at linkodas.com> <augulis.darius at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/gemini.h>
+
+#define DRAM_SET_MODE GEMINI_SET_MODE | GEMINI_MODE_DDRAM | \
+ GEMINI_CAS_3 | GEMINI_BL_4
+#define DRAM_SET_TYPE GEMINI_BUS_32b | GEMINI_RAM_15x10_16x10
+
+#define DRAM_IOCAP GEMINI_IOCAP_DRAM_CLOCK | GEMINI_IOCAP_DRAM_DATA | \
+ GEMINI_IOCAP_DRAM_CTRL
+#define DRAM_TIMING GEMINI_RRATE_AREF8 | GEMINI_RTIMER(195) | \
+ GEMINI_TRFC(11) | GEMINI_TRAS(6) | GEMINI_TWR(3) | \
+ GEMINI_TRP(3) | GEMINI_TRCD(3) | GEMINI_TCAS(3)
+#define DRAM_READ_DLL GEMINI_RDLL_BYTE3(8) | GEMINI_RDLL_BYTE2(8) | \
+ GEMINI_RDLL_BYTE1(8) | GEMINI_RDLL_BYTE0(8)
+#define DRAM_WRITE_DLL GEMINI_WDLL(26)
+#define DRAM_MEM_CTRL GEMINI_TRAINING_MODE | GEMINI_DQS_N_FALLING | \
+ GEMINI_BUF_IN_4rd | (1 << 6)
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* DRAM init */
+ ldr r0, =GEMINI_DRAM_TYPE /* DRAM set type */
+ ldr r1, =DRAM_SET_TYPE /* 32bit, 64 Mbytes total */
+ str r1, [r0]
+
+ ldr r0, =GEMINI_DRAM_MODE /* DRAM set mode */
+ ldr r1, =DRAM_SET_MODE /* DDRAM, CAS 3, Burst 4 */
+ str r1, [r0]
+
+ ldr r3, =GEMINI_GLOBAL_ID /* Global ID reg */
+ ldr r4, [r3]
+ ldr r5, =0xFF /* Chip revision mask */
+ and r4, r4, r5
+ cmp r4, #0xc0 /* Test if chip rev. is 'c0' */
+ bne end_prefetch
+
+ /* Fix for rev. 'c0' chip */
+ ldr r0, =GEMINI_DRAM_AHB_CTRL /* AHB control */
+ ldr r5, =GEMINI_WRITE_FLUSH_READ
+ str r5, [r0]
+
+end_prefetch:
+ ldr r3, =GEMINI_GLOBAL_PLL /* Mistery PLL config */
+ ldr r4, [r3]
+ orr r4, r4, #GEMINI_PLL_CHARGE_PUMP2
+ str r4, [r3]
+
+ ldr r3, =GEMINI_GLOBAL_IO_PAD /* Mistery IO pad config */
+ ldr r4, [r3]
+ ldr r5, =DRAM_IOCAP
+ orr r4, r4, r5
+ str r4, [r3]
+
+ ldr r0, =GEMINI_DRAM_TIMING /* DRAM set timing */
+ ldr r1, =DRAM_TIMING
+ str r1, [r0]
+
+ ldr r0, =GEMINI_DRAM_RD_DLL /* DRAM set Read DLL delay */
+ ldr r1, =DRAM_READ_DLL
+ str r1, [r0]
+
+ ldr r0, =GEMINI_DRAM_WR_DLL /* DRAM set Write DLL delay */
+ ldr r1, =DRAM_WRITE_DLL
+ str r1, [r0]
+
+ ldr r0, =GEMINI_DRAM_MEM_CTRL /* DRAM training mode, timing */
+ ldr r1, =DRAM_MEM_CTRL
+ str r1, [r0]
+
+ ldr r2, =GEMINI_DRAM_BASE
+ mov r4, #0xa0
+
+read_loop:
+ ldr r3, [r2] /* Read data */
+ subs r4, r4, #1 /* Decrement loop count */
+ bge read_loop
+
+ bic r1, r1, #GEMINI_TRAINING_MODE /* Disable train mode */
+ str r1, [r0]
+
+ mov pc, lr
diff --git a/board/nas4220/nas4220.c b/board/nas4220/nas4220.c
new file mode 100644
index 0000000..784a249
--- /dev/null
+++ b/board/nas4220/nas4220.c
@@ -0,0 +1,75 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <daugulis at linkodas.com> <augulis.darius at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/gemini.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PINS (GEMINI_PIN_UART_RX | GEMINI_PIN_UART_TX)
+#define MISC_CTRL (GEMINI_PAD_SFLASH_DIS | GEMINI_PAD_NAND_DIS)
+
+int board_init(void)
+{
+ /* Bypass UART pins */
+ GEMINI_GPIO_BYPASS(0) |= UART_PINS;
+
+ /* Enable: parallel flash pins, disable: serial, nand pins */
+ GEMINI_GLOBAL_MISC = MISC_CTRL;
+
+ /* Enable parallel flash direct write mode */
+ GEMINI_FLASH_PAR_ACCESS |= GEMINI_PFLASH_DWR;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ int cpu_id, cpu_rev, cpu_clk, ahb_clk;
+
+ cpu_id = GEMINI_CHIP_ID;
+ cpu_rev = GEMINI_CHIP_REV;
+ ahb_clk = GEMINI_AHB_CLK;
+
+ switch (GEMINI_CPU_AHB_RATIO) {
+ case 0:
+ cpu_clk = ahb_clk;
+ break;
+ case 1:
+ cpu_clk = (ahb_clk * 3) / 2;
+ break;
+ case 2:
+ cpu_clk = (ahb_clk * 24) / 13;
+ break;
+ case 3:
+ cpu_clk = ahb_clk * 2;
+ break;
+ default:
+ cpu_clk = 0;
+ break;
+ }
+
+ printf("\nRaidsonic ICYBOX NAS4220 board\n");
+ printf("CPU: Gemini CS%X, REV: %X\n", cpu_id, cpu_rev);
+ printf("CPU Speed: %d MHz, AHB Speed: %d MHz, APB Speed: %d MHz\n\n", cpu_clk / 1000000, ahb_clk / 1000000, ahb_clk / 6000000);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
diff --git a/board/nas4220/u-boot.lds b/board/nas4220/u-boot.lds
new file mode 100644
index 0000000..7d249c3
--- /dev/null
+++ b/board/nas4220/u-boot.lds
@@ -0,0 +1,48 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <daugulis at linkodas.com> <augulis.darius at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ board/nas4220/libnas4220.a (.text)
+ lib_arm/libarm.a (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) . = ALIGN(4); }
+ _end = .;
+}
diff --git a/cpu/arm920t/gemini/Makefile b/cpu/arm920t/gemini/Makefile
new file mode 100644
index 0000000..ca262e3
--- /dev/null
+++ b/cpu/arm920t/gemini/Makefile
@@ -0,0 +1,38 @@
+#
+# (c) Copyright 2009
+# Linkodas, Inc.
+# http://www.linkodas.com
+#
+# Author: Darius Augulis <daugulis at linkodas.com> <augulis.darius at gmail.com>
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS += timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm920t/gemini/timer.c b/cpu/arm920t/gemini/timer.c
new file mode 100644
index 0000000..ec24cd8
--- /dev/null
+++ b/cpu/arm920t/gemini/timer.c
@@ -0,0 +1,93 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <daugulis at linkodas.com> <augulis.darius at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_GEMINI
+
+#include <asm/arch/gemini.h>
+
+static ulong gemini_usec;
+static ulong timestamp;
+static ulong extraticks;
+
+int timer_init(void)
+{
+ gemini_usec = GEMINI_APB_CLK / 1000000;
+ timestamp = extraticks = 0;
+
+ GEMINI_TIMER_COUNT(0) = 0;
+ GEMINI_TIMER_LOAD(0) = 0;
+ GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0);
+
+ return 0;
+}
+
+void reset_timer(void)
+{
+ GEMINI_TIMER_CR &= ~TIMER_CR_ENABLE(0);
+ GEMINI_TIMER_COUNT(0) = 0x0;
+ GEMINI_TIMER_LOAD(0) = 0x0;
+ GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0);
+
+ timestamp = extraticks = 0;
+}
+
+unsigned long long get_usecs(void)
+{
+ ulong timenow = GEMINI_TIMER_COUNT(0);
+
+ if (timenow >= timestamp)
+ timestamp += timenow - extraticks;
+ else
+ timestamp += 0xFFFFFFFF - extraticks + timenow;
+ extraticks = timenow;
+
+ return timestamp / gemini_usec;
+}
+
+ulong get_timer(ulong base)
+{
+ return (get_usecs() / 1000) - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+void udelay(unsigned long usec)
+{
+ signed long elapsed;
+ ulong timestart = get_usecs();
+
+ do {
+ ulong timenow = get_usecs();
+ elapsed = timenow - timestart;
+ } while (elapsed < usec);
+}
+
+ulong get_tbclk(void)
+{
+ ulong tbclk;
+
+ tbclk = CONFIG_SYS_HZ;
+
+ return tbclk;
+}
+
+void reset_cpu(ulong ignored)
+{
+ GEMINI_GLOBAL_RESET = GEMINI_SOFT_RESET | GEMINI_CPU1_RESET;
+}
+
+#endif /* defined (CONFIG_GEMINI) */
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 475cdaf..761753e 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -115,8 +115,10 @@ start_code:
orr r0,r0,#0xd3
msr cpsr,r0
- bl coloured_LED_init
- bl red_LED_on
+#ifndef CONFIG_GEMINI
+ bl coloured_LED_init
+ bl red_LED_on
+#endif
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/*
@@ -189,6 +191,11 @@ relocate: /* relocate U-Boot to RAM */
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
+#ifdef CONFIG_GEMINI
+ orr r0, r0, #CONFIG_SYS_FLASH_BASE
+ orr r2, r2, #CONFIG_SYS_FLASH_BASE
+#endif
+
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
diff --git a/include/asm-arm/arch-gemini/gemini.h b/include/asm-arm/arch-gemini/gemini.h
new file mode 100644
index 0000000..e4fa91a
--- /dev/null
+++ b/include/asm-arm/arch-gemini/gemini.h
@@ -0,0 +1,271 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <daugulis at linkodas.com> <augulis.darius at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASSEMBLY__
+# define REG8(x) (*(volatile u8 *)(x))
+# define REG16(x) (*(volatile u16 *)(x))
+# define REG32(x) (*(volatile u32 *)(x))
+#else
+# define REG8(x) (x)
+# define REG16(x) (x)
+# define REG32(x) (x)
+#endif
+
+/*
+ * Memory Map definitions
+ */
+#define GEMINI_SRAM_BASE 0x00000000
+#define GEMINI_DRAM_BASE 0x10000000
+#define GEMINI_FLASH_BASE 0x30000000
+
+/*
+ * Register Map definitions
+ */
+#define GEMINI_GLOBAL_BASE 0x40000000
+#define GEMINI_WAQTCHDOG_BASE 0x41000000
+#define GEMINI_UART_BASE 0x42000000
+#define GEMINI_TIMER_BASE 0x43000000
+#define GEMINI_LCD_BASE 0x44000000
+#define GEMINI_RTC_BASE 0x45000000
+#define GEMINI_SATA_BASE 0x46000000
+#define GEMINI_LPC_HOST_BASE 0x47000000
+#define GEMINI_LPC_IO_BASE 0x47800000
+#define GEMINI_INTERRUPT_BASE 0x48000000
+#define GEMINI_SSP_CTRL_BASE 0x4A000000
+#define GEMINI_POWER_CTRL_BASE 0x4B000000
+#define GEMINI_CIR_BASE 0x4C000000
+#define GEMINI_GPIO_BASE 0x4D000000
+#define GEMINI_PCI_IO_BASE 0x50000000
+#define GEMINI_PCI_MEM_BASE 0x58000000
+#define GEMINI_TOE_BASE 0x60000000
+#define GEMINI_GMAC0_BASE 0x6000A000
+#define GEMINI_GMAC1_BASE 0x6000E000
+#define GEMINI_SECURITY_BASE 0x62000000
+#define GEMINI_IDE0_BASE 0x63000000
+#define GEMINI_IDE1_BASE 0x63400000
+#define GEMINI_RAID_BASE 0x64000000
+#define GEMINI_FLASH_CTRL_BASE 0x65000000
+#define GEMINI_DRAM_CTRL_BASE 0x66000000
+#define GEMINI_GENERAL_DMA_BASE 0x67000000
+#define GEMINI_USB0_BASE 0x68000000
+#define GEMINI_USB1_BASE 0x69000000
+#define GEMINI_BIG_ENDIAN_BASE 0x80000000
+
+/*
+ * Global Module definitions
+ */
+
+/* Global registers */
+#define GEMINI_GLOBAL_ID REG32(GEMINI_GLOBAL_BASE + 0x00)
+#define GEMINI_GLOBAL_STATUS REG32(GEMINI_GLOBAL_BASE + 0x04)
+#define GEMINI_GLOBAL_PLL REG32(GEMINI_GLOBAL_BASE + 0x08)
+#define GEMINI_GLOBAL_RESET REG32(GEMINI_GLOBAL_BASE + 0x0C)
+#define GEMINI_GLOBAL_IO_PAD REG32(GEMINI_GLOBAL_BASE + 0x10)
+#define GEMINI_GLOBAL_MISC REG32(GEMINI_GLOBAL_BASE + 0x30)
+
+/* GEMINI_GLOBAL_ID bitfields */
+#define GEMINI_CHIP_ID ((GEMINI_GLOBAL_ID & 0xFFFFFF00) >> 8)
+#define GEMINI_CHIP_REV (GEMINI_GLOBAL_ID & 0xFF)
+
+/* GEMINI_GLOBAL_STATUS bitfields */
+
+/* GEMINI_GLOBAL_PLL bitfields */
+#define GEMINI_PLL_CHARGE_PUMP2 (7 << 12)
+
+/* GEMINI_GLOBAL_RESET bitfields */
+#define GEMINI_SOFT_RESET (1 << 31)
+#define GEMINI_CPU1_RESET (1 << 30)
+
+/* GEMINI_GLOBAL_IO_PAD bitfields */
+#define GEMINI_IOCAP_DRAM_CLOCK (0xF << 8)
+#define GEMINI_IOCAP_DRAM_DATA (0xF << 4)
+#define GEMINI_IOCAP_DRAM_CTRL (0xF << 0)
+
+/* GEMINI_GLOBAL_MISC bitfields */
+#define GEMINI_PAD_SFLASH_DIS (1 << 0)
+#define GEMINI_PAD_PFLASH_DIS (1 << 1)
+#define GEMINI_PAD_NAND_DIS (1 << 2)
+#define GEMINI_PAD_DRAM_PD_EN (1 << 3)
+#define GEMINI_PAD_IDE_EN (1 << 4)
+#define GEMINI_PAD_PCI_EN (1 << 5)
+#define GEMINI_PAD_LPC_EN (1 << 6)
+#define GEMINI_PAD_LCD_EN (1 << 7)
+#define GEMINI_PAD_SSP_EN (1 << 8)
+#define GEMINI_PAD_TVC_EN (1 << 9)
+#define GEMINI_PCI_IDLE_DETECT(x) (x << 11) /* PCI Clocks: 0 - 256, 1 - 128, 2 - 64, 3 - 32 */
+#define GEMINI_USB0_WAKE_EN (1 << 14)
+#define GEMINI_USB1_WAKE_EN (1 << 15)
+#define GEMINI_CLOCK_LPC_EN (1 << 16)
+#define GEMINI_CLOCK_PCI_EN (1 << 17)
+#define GEMINI_CLOCK_PCI66_EN (1 << 18)
+#define GEMINI_CLOCK_EXT_EN (1 << 19)
+#define GEMINI_CLOCK_TVC_EN (1 << 20)
+#define GEMINI_CLOCK_APB_EN (1 << 21)
+#define GEMINI_USB0_VBUS_EN (1 << 22)
+#define GEMINI_USB1_VBUS_EN (1 << 23)
+#define GEMINI_IDE_IO_0 (0 << 24)
+#define GEMINI_IDE_IO_1 (1 << 24)
+#define GEMINI_IDE_IO_2 (2 << 24)
+#define GEMINI_IDE_IO_3 (3 << 24)
+#define GEMINI_GMAC_IO_0 (0 << 27)
+#define GEMINI_GMAC_IO_1 (1 << 27)
+#define GEMINI_GMAC_IO_2 (2 << 27)
+#define GEMINI_USB0_PLUG (1 << 29) /* 0 - miniA, 1 - miniB */
+#define GEMINI_USB1_PLUG (1 << 30) /* 0 - miniA, 1 - miniB */
+#define GEMINI_MEMORY_SWAP (1 << 31)
+
+/*
+ * DRAM Module definitions
+ */
+
+/* DRAM registers */
+#define GEMINI_DRAM_MODE REG32(GEMINI_DRAM_CTRL_BASE + 0x00)
+#define GEMINI_DRAM_TIMING REG32(GEMINI_DRAM_CTRL_BASE + 0x04)
+#define GEMINI_DRAM_MEM_CTRL REG32(GEMINI_DRAM_CTRL_BASE + 0x08)
+#define GEMINI_DRAM_TYPE REG32(GEMINI_DRAM_CTRL_BASE + 0x0C)
+#define GEMINI_DRAM_ARBITER REG32(GEMINI_DRAM_CTRL_BASE + 0x10)
+#define GEMINI_DRAM_RD_DLL REG32(GEMINI_DRAM_CTRL_BASE + 0x14)
+#define GEMINI_DRAM_WR_DLL REG32(GEMINI_DRAM_CTRL_BASE + 0x18)
+#define GEMINI_DRAM_AHB_CTRL REG32(GEMINI_DRAM_CTRL_BASE + 0x1C)
+#define GEMINI_DRAM_CPU_REMAP REG32(GEMINI_DRAM_CTRL_BASE + 0x40)
+
+/* GEMINI_DRAM_MODE bitfields */
+#define GEMINI_BL_4 (2 << 0) /* Burst lenght 4 */
+#define GEMINI_BL_8 (3 << 0) /* Burst lenght 8 */
+#define GEMINI_BT_INT (1 << 3) /* Burst type interleave */
+#define GEMINI_CAS_2 (2 << 4) /* CAS latency 2 */
+#define GEMINI_CAS_3 (3 << 4) /* CAS latency 3 */
+#define GEMINI_CAS_25 (6 << 4) /* CAS latency 2.5 */
+#define GEMINI_MODE_SDRAM (0 << 7) /* Mode SDRAM */
+#define GEMINI_MODE_DDRAM (2 << 7) /* Mode DDRAM */
+#define GEMINI_WBL_BURST (0 << 9) /* Write Burst */
+#define GEMINI_WBL_SINGLE (1 << 9) /* Write Single */
+#define GEMINI_DLL_DISABLE (1 << 16) /* DLL disable */
+#define GEMINI_DRIVING_REDUCED (1 << 17) /* Driving Strength */
+#define GEMINI_SET_MODE (1 << 31) /* Set Mode Register */
+
+/* GEMINI_DRAM_TIMING bitfields */
+#define GEMINI_RRATE_AREF8 (1 << 31) /* Refresh rate AREF 8 */
+#define GEMINI_RRATE_AREF4 (0 << 31) /* Refresh rate AREF 4 */
+#define GEMINI_RTIMER(x) (x << 16) /* Refresh timer cycles 0...0x7FFF */
+#define GEMINI_TRFC(x) (x << 12) /* SDRAM Auto-refresh cycles 0...15 */
+#define GEMINI_TRAS(x) (x << 8) /* SDRAM TRAS cycles 0...15 */
+#define GEMINI_TWR(x) (x << 6) /* SDRAM TWR cycles 0...3 */
+#define GEMINI_TRP(x) (x << 4) /* SDRAM TRP cycles 0...3 */
+#define GEMINI_TRCD(x) (x << 2) /* SDRAM TRCD cycles 0...3 */
+#define GEMINI_TCAS(x) (x << 0) /* SDRAM TCAS cycles 0...3 */
+
+/* GEMINI_DRAM_MEM_CTRL bitfields */
+#define GEMINI_TRAINING_MODE (1 << 0) /* DRAM training mode */
+#define GEMINI_DQS_N_RISING (0 << 1) /* Read DQS Lock Window for CL 2, 3 */
+#define GEMINI_DQS_L_RISING (1 << 1) /* Read DQS Lock Window for CL 3 */
+#define GEMINI_DQS_N_FALLING (2 << 1) /* Read DQS Lock Window for CL 2.5 */
+#define GEMINI_DQS_L_FALLING (3 << 1) /* Read DQS Lock Window for CL 2.5 */
+
+#define GEMINI_BUF_IN_3rd (0 << 4) /* capture at 3rd T after read command */
+#define GEMINI_BUF_IN_4rd (1 << 4) /* capture at 4rd T after read command */
+#define GEMINI_BUF_IN_5rd (2 << 4) /* capture at 5rd T after read command */
+#define GEMINI_BUF_IN_6rd (3 << 4) /* capture at 6rd T after read command */
+
+/* GEMINI_DRAM_TYPE bitfields */
+#define GEMINI_BUS_16b (1 << 30) /* DRAM bus is 16 bit */
+#define GEMINI_BUS_32b (0 << 30) /* DRAM bus is 32 bit */
+
+/* (bank address + row address) x (column address) */
+#define GEMINI_RAM_14x8 (0 << 0)
+#define GEMINI_RAM_14x9_15x9 (1 << 0)
+#define GEMINI_RAM_15x10_16x10 (2 << 0)
+#define GEMINI_RAM_15x11_16x11 (3 << 0)
+
+/* GEMINI_DRAM_RD_DLL bitfields */
+#define GEMINI_RDLL_BYTE3(x) (x << 24) /* Delay of byte 3 cycles 0...63 */
+#define GEMINI_RDLL_BYTE2(x) (x << 16) /* Delay of byte 2 cycles 0...63 */
+#define GEMINI_RDLL_BYTE1(x) (x << 8) /* Delay of byte 1 cycles 0...63 */
+#define GEMINI_RDLL_BYTE0(x) (x << 0) /* Delay of byte 0 cycles 0...63 */
+
+/* GEMINI_DRAM_WR_DLL bitfields */
+#define GEMINI_WDLL(x) (x << 0) /* Delay cycles 0...63 */
+
+/* GEMINI_DRAM_AHB_CTRL definitions */
+#define GEMINI_WRITE_FLUSH_READ (1 << 0)
+
+/*
+ * GPIO Module definitions
+ */
+
+/* GPIO registers */
+#define GEMINI_GPIO_X_BASE(x) (GEMINI_GPIO_BASE + (x) * 0x1000000)
+#define GEMINI_GPIO_DOUT(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x00)
+#define GEMINI_GPIO_DIN(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x04)
+#define GEMINI_GPIO_DIR(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x08)
+#define GEMINI_GPIO_BYPASS(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x0C)
+#define GEMINI_GPIO_DSET(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x10)
+#define GEMINI_GPIO_DCLEAR(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x14)
+#define GEMINI_GPIO_PULL_EN(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x18)
+#define GEMINI_GPIO_PULL_DIR(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x1C)
+#define GEMINI_GPIO_INT_EN(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x20)
+#define GEMINI_GPIO_INT_RAW(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x24)
+#define GEMINI_GPIO_INT_MASK_ST(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x28)
+#define GEMINI_GPIO_INTR_MASK(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x2C)
+#define GEMINI_GPIO_INT_CLR(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x30)
+#define GEMINI_GPIO_INT_TRIG(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x34)
+#define GEMINI_GPIO_INTR_BOTH(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x38)
+#define GEMINI_GPIO_INTR_EDGE(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x3C)
+#define GEMINI_GPIO_BNC_EN(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x40)
+#define GEMINI_GPIO_BNC_PRESC(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x44)
+
+/* GPIO pins definitions */
+#define GEMINI_PIN_UART_RX (1 << 9)
+#define GEMINI_PIN_UART_TX (1 << 10)
+
+/*
+ * FLASH Module definitions
+ */
+
+/* FLASH registers */
+#define GEMINI_FLASH_PAR_ACCESS REG32(GEMINI_FLASH_CTRL_BASE + 0x20)
+
+/* GEMINI_FLASH_PAR_ACCESS */
+#define GEMINI_PFLASH_DWR (1 << 14)
+
+/*
+ * TIMER Module definitions
+ */
+
+/* Timer registers */
+#define GEMINI_TIMER_X_BASE(x) (GEMINI_TIMER_BASE + (0 + x * 0x10))
+#define GEMINI_TIMER_COUNT(x) REG32(GEMINI_TIMER_X_BASE(x) + 0x00)
+#define GEMINI_TIMER_LOAD(x) REG32(GEMINI_TIMER_X_BASE(x) + 0x04)
+#define GEMINI_TIMER_MATCH1(x) REG32(GEMINI_TIMER_X_BASE(x) + 0x08)
+#define GEMINI_TIMER_MATCH2(x) REG32(GEMINI_TIMER_X_BASE(x) + 0x0C)
+#define GEMINI_TIMER_CR REG32(GEMINI_TIMER_BASE + 0x30)
+
+/* Timer bitfields */
+#define TIMER_CR_ENABLE(x) (1 << (0 + x * 3))
+#define TIMER_CR_CLOCK(x) (1 << (1 + x * 3))
+#define TIMER_CR_INT(x) (1 << (2 + x * 3))
+#define TIMER_CR_UP(x) (1 << (9 + x))
+
+/*
+ * Helper Macros
+ */
+#define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130)
+
+/* System clocks */
+#define GEMINI_SYS_CLK (REG_TO_AHB_SPEED(GEMINI_GLOBAL_STATUS) * 1000000)
+#define GEMINI_CPU_AHB_RATIO ((GEMINI_GLOBAL_STATUS >> 18) & 3)
+
+#define GEMINI_AHB_CLK GEMINI_SYS_CLK
+#define GEMINI_APB_CLK (GEMINI_SYS_CLK / 6)
+#define GEMINI_UART_CLK 48000000
+
diff --git a/include/configs/nas4220.h b/include/configs/nas4220.h
new file mode 100644
index 0000000..7f089c6
--- /dev/null
+++ b/include/configs/nas4220.h
@@ -0,0 +1,116 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <daugulis at linkodas.com> <augulis.darius at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/* This is U-boot configuration for Raidsonic ICYBOX NAS4220 board.
+ * More information about this device is available on websites:
+ * http://en.nas-4220.org
+ * http://wiki.gpl-devices.org/wiki/Raidsonic_ICY-BOX_IB-NAS4220-B
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/gemini.h>
+#include <asm-arm/sizes.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM920T 1
+#define CONFIG_GEMINI 1
+#define CONFIG_NAS4220 1
+#undef CONFIG_USE_IRQ
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550 1
+#define CONFIG_SYS_NS16550_SERIAL 1
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK GEMINI_UART_CLK
+#define CONFIG_SYS_NS16550_COM1 GEMINI_UART_BASE
+#define CONFIG_CONS_INDEX 1
+
+/* Select serial console configuration */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_ECHO /* echo arguments */
+#define CONFIG_CMD_SAVEENV /* saveenv */
+#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#define CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_ITEST /* Integer (and string) test */
+#define CONFIG_CMD_LOADB /* loadb */
+#define CONFIG_CMD_LOADS /* loads */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC /* Misc functions like sleep etc */
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SOURCE /* "source" command support */
+#define CONFIG_CMD_XIMG /* Load part of Multi Image */
+
+#define CONFIG_BOOTDELAY 10
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=64M"
+#define CONFIG_BOOTFILE "nas4220"
+#define CONFIG_BOOTCOMMAND "bootm"
+
+/* Miscellaneous configurable options */
+#define BOARD_LATE_INIT 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_SYS_PROMPT "NAS4220$ "
+
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR 0x10500000
+#define CONFIG_SYS_HZ 1000
+
+/* Stack size */
+#define CONFIG_STACKSIZE SZ_512K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 GEMINI_DRAM_BASE
+#define PHYS_SDRAM_1_SIZE SZ_64M /* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + SZ_4M) /* 60 MB test */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+
+/* FLASH configuration */
+#define CONFIG_SYS_FLASH_BASE GEMINI_FLASH_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+/* Environment configuration
+ * We have 128 flash sectors, each of 128 KB.
+ * Environment is stored in last 8 KB on the flash
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN SZ_128K
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0xFFE000 /* Last 8K on the flash */
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_SECT_SIZE SZ_128K
+
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/* CFI FLASH driver setup */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#endif /* __CONFIG_H */
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