[U-Boot] 460GT PCIe configuration

[Leon Woestenberg]

Hello Vadim, Stefan,

On Wed, Jan 14, 2009 at 5:42 PM, vb <vb at vsbe.com> wrote:
> On Wed, Jan 14, 2009 at 7:03 AM, Stefan Roese <sr at denx.de> wrote:
>> On Tuesday 13 January 2009, vb wrote:
>>
>>> I have several different targets with different PCIe components, but
>>> all using the same base CPU subsystem design, and on some of them PCIe
>>> components misbehave, namely, PCIe memory read transactions fail with
>>> a machine check after a timeout, even though the PCIe side of things
>>> is fine (when looking with a protocol analyzer).
>>
> on our own design). The one which fails is based on the very similar
> 460GT based platform, but uses an Altera FPGA with a standard Altera
> PCIe interface implementation.
>
> What happens is that config space transactions (both read and write)
> and memory writes work fine, but attempts to read Altera's memory
> mapped space causes a machine check with very vague error reporting.
>

Vadim, I am currently designing a Altera FPGA PCIe application and
testing on the AMCC460EX as one of the targets, so I may provide some
hints on where to look. I debugged *without* protocol analyser and
also hit some emachine check exceptions when the FPGA logic was still
misbehaving.

Let me just throw some hints and references your way, hope they might be useful:

Do you use a reference design?
Does the FPGA application respond to the reads?
Do you map the BARs correctly?
Do you use 32-bit read/writes, 32-bit alignment?

In the linux-next GIT tree, my driver for the Altera PCIe Chaining DMA
design is included:
drivers/staging/altpciechdma/altpciechdma.c

Best regards,
-- 
Leon