[U-Boot] DDR2 configuration in MPC85xx

Liu Dave-R63238 DaveLiu at freescale.com
Fri May 15 02:59:30 CEST 2009


 
> > The tlb settings looks fine (debbug in setup_ddr_tlbs()):
> >
> > ram_tlb_address: 0x0, ram_tlb_address: 0x0, ram_tlb_index: 
> 0x8, tlb_size:
> 0xa
> > ram_tlb_address: 0x40000000, ram_tlb_address: 0x40000000, 
> ram_tlb_index:
> 0x9, tlb_size: 0xa
> 
> "tlb_size: 0xa" is _not_ fine.
> 

No, TLB_SIZE = 0xa is fine for 8548.
That is e500v2 core.


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