[U-Boot] uBoot Debug: GPIO Toggling does not working over 8536DS uboot

AgarwalAshish ashish.g at teldevice.co.jp
Thu May 21 10:01:25 CEST 2009


Project details: 

CPU: MPC8536DS [Core E500, Freescale]
Flash: 16MB [50MHz Local bus Clk)
DDR: 1G (SODIMM, 400 MHz)
Baord: Network Evaluation Cutom MPC8536E Board

U-Boot Debug Issue (GPIO Toggling code help)
_________________________

-> as i am not able to debug uboot over jtag and the CW tool till now,  [MPC8536 CPU Suoort to the CW is not available now it will be released in future.]

so i have to debug it via the printf statments meanwhile after the UART initialization get over.
But till when the UART initialization is not done so ihave to check the Uboot process via the GPIO Togging. ;)

So when i wrote u-boot.bin file to the Flash via Jtag CW FlashProgrammer tool, and power on the SW of te board it does not bootup and the GPIO toggling is not over yet what i have to do .. 
is my code to toggle the GPIO is wrong or i am mistaking anything. (This code i am testing over MPC8536DS Calamari baord, not working there too)

/cpu/mpc85xx/statrt.S

.....
....
	.section .bootpg,"ax"
	.globl _start_e500

_start_e500:

/* 20090520 DEBUG LED Code start */
	lis r2,ADR_CFG_GPIO at h
	ori r2,r2,ADR_CFG_GPIO at l

	lis r3,DIR_GPIO at h
	ori r3,r3,DIR_GPIO at l

	stw r3,0(r2)
	isync
	msync

	lis r2,ADR_GPIO at h
	ori r2,r2,ADR_GPIO at l

	lis r3,DAT_GPIO at h
	ori r3,r3,DAT_GPIO at l
	isync
	msync

_T_LED:
	/* xori r1,r1,0xFFFF */
	stw  r3,0(r2)
	isync
	msync
	b    _T_LED
/*  TED 20090520 DEBUG LED Code End */

/* clear registers/arrays not reset by hardware */

	/* L1 */
	li	r0,2
	mtspr	L1CSR0,r0	/* invalidate d-cache */
	mtspr	L1CSR1,r0	/* invalidate i-cache */

	mfspr	r1,DBSR
	mtspr	DBSR,r1		/* Clear all valid bits */
.....
....

and i declared the used macro in the file 
./include/configs/MPC8536DS.h

.......
....

#define ADR_CFG_GPIO		0xFF70FC00		/* GPIO LED Configuration Register address */
#define ADR_GPIO		0xFF70FC08		/* GPIO LED Data Register */
#define DIR_GPIO		0xFFFFFFFF		/* GPIO DIRECTION though it is GPIO [0-15] */
#define DAT_GPIO		0xF28FF28F              /* GPIO Data GPIO[6-8] will set as toggle alternate */

.....
........

i tried setting as too 
#define DIR_GPIO		0x03800000		/* Only GPIO[6:8] */
#define DAT_GPIO		0x02800000

But not workied for me :( 

isync msync too not worked i put this after I cache D Cache disable too 

please suggest me how to debug the GPIO toggling code and the process of debugging uboot.
-> also suggest me any Application note or manual over the PPC Assembly coding manual.


* In case we cannot put this code here so what is the method to check the Uboot activity following like 
   till where uboot does well or it hangs arround and after this and that kind of stuff?
  and from when we can do toggling the GPIO's
----------------------------------------------------------------------------------------

waiting for the reply this time more eagerly ..W.w.W..

---
Ashish Agarwal


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