[U-Boot] Enabling D cache on Arm Cortex A8 in U-boot

[akshay ts]

Hi,
I want to enable D/I Cache in ARM Cortex, whenever i enable cache bit in control register, system hangs. I feel i dont have to flush the cache since u-boot in single threaded app. 
Can u please let me know the steps to be followed to enable. 
I have enabled MMU  and it is working fine. I have set cacheable/bufferable bit in translation table descriptors. TEX bit is 0. As of now i am using only sections.

Warm Regards,
Akshay


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