[U-Boot] [PATCH] ppc/85xx: Fix LCRR_CLKDIV defines

[Kumar Gala]

For some reason the CLKDIV field varies between SoC in how it interprets
the bit values.

All 83xx and early (e500v1) PQ3 devices support:
 clk/2: CLKDIV = 2
 clk/4: CLKDIV = 4
 clk/8: CLKDIV = 8

Newer PQ3 (e500v2) and MPC86xx support:
 clk/4: CLKDIV = 2
 clk/8: CLKDIV = 4
 clk/16: CLKDIV = 8

Ensure that the MPC86xx and MPC85xx still get the same behavior and make
the the defines reflect their logical view (not the value of the field).

Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
 include/asm-ppc/fsl_lbc.h     |    8 ++++++++
 include/configs/XPEDITE5170.h |    2 +-
 include/configs/XPEDITE5200.h |    2 +-
 include/configs/XPEDITE5370.h |    2 +-
 4 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index a28082e..08d31e1 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -311,9 +311,17 @@
  */
 #define LCRR_CLKDIV			0x0000001F
 #define LCRR_CLKDIV_SHIFT		0
+#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
+    defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
+    defined(CONFIG_MPC8560)
 #define LCRR_CLKDIV_2			0x00000002
 #define LCRR_CLKDIV_4			0x00000004
 #define LCRR_CLKDIV_8			0x00000008
+#else
+#define LCRR_CLKDIV_4			0x00000002
+#define LCRR_CLKDIV_8			0x00000004
+#define LCRR_CLKDIV_16			0x00000008
+#endif
 
 /* LTEDR - Transfer Error Check Disable Register
  */
diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 242466a..30642cd 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -122,7 +122,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
  */
 
-#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_2 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_4 | LCRR_EADC_3)
 
 /*
  * NAND flash configuration
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index deda208..d79231b 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -103,7 +103,7 @@
  * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
  */
 
-#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
 
 /*
  * NAND flash configuration
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 3c58ebe..65e1afd 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -116,7 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
  */
 
-#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
 
 /*
  * NAND flash configuration
-- 
1.6.0.6