[U-Boot] [PATCH 6/7] ppc/p4080: Handle timebase enabling and frequency reporting

[Scott Wood]

Kumar Gala wrote:
> On CoreNet style platforms the timebase frequency is the bus frequency
> defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
> the core not longer controls the enabling of the timebase.  We now need
> to enable the boot core's timebase via CCSR register writes.
> 
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> ---
>  cpu/mpc85xx/cpu.c      |    4 ++++
>  cpu/mpc85xx/cpu_init.c |   12 ++++++++++++
>  cpu/mpc85xx/fdt.c      |    7 ++++++-
>  3 files changed, 22 insertions(+), 1 deletions(-)
> 
> diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
> index bdd9ee4..25c0416 100644
> --- a/cpu/mpc85xx/cpu.c
> +++ b/cpu/mpc85xx/cpu.c
> @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
>   */
>  unsigned long get_tbclk (void)
>  {
> +#ifdef CONFIG_FSL_CORENET
> +	return (gd->bus_clk + 8) / 16;
> +#else
>  	return (gd->bus_clk + 4UL)/8UL;
> +#endif
>  }
[snip]
> +#ifdef CONFIG_FSL_CORENET
> +	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> +		"timebase-frequency", bd->bi_busfreq / 16, 1);
> +#else
>  	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
>  		"timebase-frequency", bd->bi_busfreq / 8, 1);
> +#endif

We could just use get_tbclk() here and not have to maintain the 
knowledge in two places.

-Scott