[U-Boot] [PATCH] ppc4xx: Netstal boards: various cleanups
Stefan Roese
sr at denx.de
Wed Sep 23 18:57:57 CEST 2009
Hi Niklaus,
On Wednesday 23 September 2009 17:22:49 Niklaus Giger wrote:
> Various cleanups for our boards:
> - vxworks_preboot to get clock input right for HCU4/MCU25
> - reboot if SW-install-input is activated
> - clear vxWorks exception msg
> - HCU5: various HW-registers updated
> - HCU5: 2nd Ethernet = SMII, Ethernet PLL Config. = recommended values
> - HCU5: PATCH HAB: WRITE PIPELINING OFF
> - HCU5: no pci_init if board has no PCI
> - MCU25: corrected address to read slot id
> - Lindent -pcs for hcu5.c
Please find some comments below.
> Signed-off-by: Niklaus Giger <niklaus.giger at netstal.com>
> ---
> board/netstal/common/nm.h | 3 +
> board/netstal/common/nm_bsp.c | 14 ++++
> board/netstal/hcu4/hcu4.c | 9 +++
> board/netstal/hcu5/hcu5.c | 150
> ++++++++++++++++++++++++++++------------- board/netstal/hcu5/sdram.c |
> 128 +++++++++++++++++++++++------------ board/netstal/mcu25/mcu25.c |
> 5 +-
> 6 files changed, 216 insertions(+), 93 deletions(-)
>
> diff --git a/board/netstal/common/nm.h b/board/netstal/common/nm.h
> index 3dff1d6..128b0c3 100644
> --- a/board/netstal/common/nm.h
> +++ b/board/netstal/common/nm.h
> @@ -18,12 +18,15 @@
> * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
> 02111-1307, USA */
>
> +#include <exports.h>
> +
> extern void hcu_led_set(u32 value);
> extern u32 get_serial_number(void);
> extern u32 hcu_get_slot(void);
> extern int board_with_pci(void);
> extern void nm_show_print(int generation, int index, int hw_capabilities);
> extern void set_params_for_sw_install(int install_requested, char
> *board_name ); +extern int sys_install_requested(void);
> extern void common_misc_init_r(void);
>
> enum {
> diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c
> index 237f4ed..e22cc58 100644
> --- a/board/netstal/common/nm_bsp.c
> +++ b/board/netstal/common/nm_bsp.c
> @@ -37,6 +37,7 @@ generation_info generations[6] = {
> {HW_GENERATION_MCU20, "MCU20"},
> {HW_GENERATION_MCU25, "MCU25"},
> };
> +static int installRequested;
>
> void nm_show_print(int generation, int index, int hw_capabilities)
> {
> @@ -60,6 +61,7 @@ void nm_show_print(int generation, int index, int
> hw_capabilities)
>
> void set_params_for_sw_install(int install_requested, char *board_name )
> {
> + memset((void *)0x4300, 0, 0x100); /* clear vxWorks exception msg */
> if (install_requested) {
> char string[128];
>
> @@ -115,3 +117,15 @@ void common_misc_init_r(void)
> saveenv();
> }
> }
> +
> +void show_activity(int arg)
> +{
> + hcu_led_set(arg);
> + if( sys_install_requested() !=installRequested )
> + {
if (sys_install_requested() != installRequested ) {
> + printf("%s: installRequested 0x%x 0x%x\n", __FUNCTION__,
> + installRequested,
> + sys_install_requested());
> + do_reset ();
do_reset();
> + }
> +}
> diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c
> index 40bec8e..75be92e 100644
> --- a/board/netstal/hcu4/hcu4.c
> +++ b/board/netstal/hcu4/hcu4.c
> @@ -48,6 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;
> */
> #define CPC0_CR0_VALUE 0x0030103c
> #define CPC0_CR1_VALUE 0x00004051
> +#define CPCO_CR1_USE_EXTERNAL 0x00804051
>
> int board_early_init_f (void)
> {
> @@ -154,6 +155,14 @@ int misc_init_r(void)
> return 0;
> }
>
> +int vxworks_preboot(void) {
> + if (sys_install_requested())
> + {
> + mtdcr(CPC0_CR1, CPCO_CR1_USE_EXTERNAL);
> + }
if (sys_install_requested())
mtdcr(CPC0_CR1, CPCO_CR1_USE_EXTERNAL);
> + return 0;
> +}
> +
> phys_size_t initdram(int board_type)
> {
> long dram_size = 0;
> diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
> index 836c034..46eb9d1 100644
> --- a/board/netstal/hcu5/hcu5.c
> +++ b/board/netstal/hcu5/hcu5.c
> @@ -45,6 +45,9 @@ extern flash_info_t
> flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define
> HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000)
> #define HCU_SW_INSTALL_REQUESTED 0x10
>
> +#define OPB2PLB40_BCTRL 0x350
> +#define P4P3BO0_CFG 0x026
> +
> /*
> * This function is run very early, out of flash, and before devices are
> * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
> @@ -74,17 +77,17 @@ int board_early_init_f(void)
>
> mfcpr(CPR0_ICFG, cpr0icfg);
> if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
> - mtcpr(CPR0_MALD, 0x02000000);
> - mtcpr(CPR0_OPBD, 0x02000000);
> - mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
> - mtcpr(CPR0_PLLC, 0x40000238);
> - mtcpr(CPR0_PLLD, 0x01010414);
> + mtcpr(CPR0_MALD, 0x02000000);
> + mtcpr(CPR0_OPBD, 0x02000000);
> + mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
> + mtcpr(CPR0_PLLC, 0x40000238);
> + mtcpr(CPR0_PLLD, 0x01010414);
> mtcpr(CPR0_PRIMAD, 0x01000000);
> mtcpr(CPR0_PRIMBD, 0x01000000);
> - mtcpr(CPR0_SPCID, 0x03000000);
> - mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
> - mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
> - mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
> + mtcpr(CPR0_SPCID, 0x03000000);
> + mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
> + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1 */
> + mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
>
> /*
> * Initiate system reset in debug control register DBCR
> @@ -92,7 +95,7 @@ int board_early_init_f(void)
> dbcr = mfspr(SPRN_DBCR0);
> mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
> }
> - mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
> + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1 */
> #endif
> mtdcr(EBC0_CFGADDR, EBC0_CFG);
> mtdcr(EBC0_CFGDATA, 0xb8400000);
> @@ -155,6 +158,9 @@ int board_early_init_f(void)
> mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */
> mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */
>
> + /* 2nd Ethernet = SMII, Ethernet PLL Config. = recommended values */
> + mtsdr(SDR0_PFC2, 0x4642DB00);
> +
> /* setup BOOT FLASH */
> mtsdr(SDR0_CUST0, 0xC0082350);
>
> @@ -220,7 +226,6 @@ u32 get_serial_number(void)
> return in_be32(serial);
> }
>
> -
> /*
> * hcu_get_slot
> */
> @@ -230,7 +235,6 @@ u32 hcu_get_slot(void)
> return in_be16(slot) & 0x7f;
> }
>
> -
> /*
> * misc_init_r.
> */
> @@ -239,6 +243,7 @@ int misc_init_r(void)
> unsigned long usb2d0cr = 0;
> unsigned long usb2phy0cr, usb2h0cr = 0;
> unsigned long sdr0_pfc1;
> + unsigned long addr;
>
> #ifdef CONFIG_ENV_IS_IN_FLASH
> /* Monitor protection ON by default */
> @@ -251,7 +256,8 @@ int misc_init_r(void)
> /* Env protection ON by default */
> (void)flash_protect(FLAG_PROTECT_SET,
> CONFIG_ENV_ADDR_REDUND,
> - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
> + CONFIG_ENV_ADDR_REDUND +
> + 2 * CONFIG_ENV_SECT_SIZE -1,
> &flash_info[0]);
> #endif
> #endif
> @@ -266,59 +272,101 @@ int misc_init_r(void)
> mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
> mfsdr(SDR0_USB2H0CR, usb2h0cr);
>
> - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
> - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
> - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
> - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
> - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
> - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
> - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
> - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
> - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
> - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
> + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
> + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
> + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
> + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1 */
> + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
> + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
> + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
> + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */
> + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
> + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */
>
> /* An 8-bit/60MHz interface is the only possible alternative
> * when connecting the Device to the PHY
> */
> - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
> - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
> + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
> + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1 */
>
> /* To enable the USB 2.0 Device function through the UTMI interface */
> - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
> - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
> + usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
> + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1 */
>
> - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
> - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
> + sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
> + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0 */
>
> mtsdr(SDR0_PFC1, sdr0_pfc1);
> mtsdr(SDR0_USB2D0CR, usb2d0cr);
> mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
> mtsdr(SDR0_USB2H0CR, usb2h0cr);
>
> - /*clear resets*/
> + /*clear resets */
> udelay(1000);
> mtsdr(SDR0_SRST1, 0x00000000);
> udelay(1000);
> mtsdr(SDR0_SRST0, 0x00000000);
> printf("USB: Host(int phy) Device(ext phy)\n");
>
> + /* Set priority for all PLB3 devices to 2. */
> + mfsdr(SD0_AMP1, addr);
> + mtsdr(SD0_AMP1, (addr & 0xCF30B400) | 0x8A20B400);
> +
> + /* Set PLB3 arbiter to fair mode. */
> + addr = mfdcr(PLB3_ACR);
> + mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
> +
> + /*
> + * Set priority for all PLB4 devices to 2.
> + */
> + mfsdr(SD0_AMP0, addr);
> + mtsdr(SD0_AMP0, (addr & 0xFFF3FD00) | 0xAAA2FD00);
> +
> + /*
> + * Set PLB4 arbiter to:
> + * fair mode, High Bus Utilisation Enabled,
> + * 2 Deep read pipe, Write pipeline disabled.
> + */
> + addr = (mfdcr(PLB4_ACR & 0xFF000000) | 0xDA000000);
> + mtdcr(PLB4_ACR, addr);
> +
> + /*
> + * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
> + * Workaround: Disable write pipelining to DDR SDRAM by setting
> + * PLB0_ACR[WRP] = 0.
> + */
> + mtdcr(PLB0_ACR,
> + (mfdcr(PLB0_ACR) & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_DISABLED);
> +
> + /* Segment1 */
> + mtdcr(PLB1_ACR,
> + (mfdcr(PLB1_ACR) & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_DISABLED);
> +
> + /* Set priority of OPB-to-PLB4 Bridge */
> + mtdcr(OPB2PLB40_BCTRL,
> + (mfdcr(OPB2PLB40_BCTRL) & ~0xC0000000) | 0x80000000);
> +
> + /* Set priority of PLB4 to PLB3 Bridge */
> + mtdcr(P4P3BO0_CFG, (mfdcr(P4P3BO0_CFG) & ~0x00C00000) | 0x00800000);
> +
> common_misc_init_r();
> - set_params_for_sw_install( sys_install_requested(), "hcu5" );
> + set_params_for_sw_install(sys_install_requested(), "hcu5");
> /* We cannot easily enable trace before, as there are other
> * routines messing around with sdr0_pfc1. And I do not need it.
> */
> if (mfspr(SPRN_DBCR0) & 0x80000000) {
> /* External debugger alive
> * enable trace facilty for Lauterbach
> - * CCR0[DTB]=0 Enable broadcast of trace information
> - * SDR0_PFC0[TRE] Trace signals are enabled instead of
> - * GPIO49-63
> + * CCR0[DTB]=0 Enable broadcast of trace information
> + * SDR0_PFC0[TRE] Trace signals are enabled instead of
> + * GPIO49-63
> */
> - mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));
> - mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
> + mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~(CCR0_DTB));
> + mtsdr(SDR0_PFC0, SDR0_PFC1 | SDR0_PFC0_TRE_ENABLE);
> }
> return 0;
> }
> +
> #ifdef CONFIG_PCI
> int board_with_pci(void)
> {
> @@ -344,7 +392,9 @@ int pci_pre_init(struct pci_controller *hose)
> {
> unsigned long addr;
>
> - if (!board_with_pci()) { return 0; }
> + if (!board_with_pci()) {
> + return 0;
> + }
if (!board_with_pci())
return 0;
>
> /*
> * Set priority for all PLB3 devices to 0.
> @@ -353,7 +403,7 @@ int pci_pre_init(struct pci_controller *hose)
> mfsdr(SD0_AMP1, addr);
> mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
> addr = mfdcr(PLB3_ACR);
> - mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
> + mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
>
> /*
> * Set priority for all PLB4 devices to 0.
> @@ -361,17 +411,17 @@ int pci_pre_init(struct pci_controller *hose)
> mfsdr(SD0_AMP0, addr);
> mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
> addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
> - mtdcr(PLB4_ACR, addr); /* Sequoia */
> + mtdcr(PLB4_ACR, addr); /* Sequoia */
>
> /*
> * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
> * Workaround: Disable write pipelining to DDR SDRAM by setting
> * PLB0_ACR[WRP] = 0.
> */
> - mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
> + mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
>
> /* Segment1 */
> - mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
> + mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
>
> return board_with_pci();
> }
> @@ -386,14 +436,16 @@ int pci_pre_init(struct pci_controller *hose)
> */
> void pci_target_init(struct pci_controller *hose)
> {
> - if (!board_with_pci()) { return; }
> + if (!board_with_pci()) {
> + return;
> + }
if (!board_with_pci())
return;
> /*
> * Set up Direct MMIO registers
> *
> * PowerPC440EPX PCI Master configuration.
> * Map one 1Gig range of PLB/processor addresses to PCI memory space.
> * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
> - * 0xA0000000-0xDFFFFFFF
> + * 0xA0000000-0xDFFFFFFF
> * Use byte reversed out routines to handle endianess.
> * Make this region non-prefetchable.
> */
> @@ -448,7 +500,9 @@ void pci_target_init(struct pci_controller *hose)
> void pci_master_init(struct pci_controller *hose)
> {
> unsigned short temp_short;
> - if (!board_with_pci()) { return; }
> + if (!board_with_pci()) {
> + return;
> + }
Again.
>
> /*---------------------------------------------------------------
> * Write the PowerPC440 EP PCI Configuration regs.
> @@ -479,7 +533,7 @@ int is_pci_host(struct pci_controller *hose)
> {
> return 1;
> }
> -#endif /* defined(CONFIG_PCI) */
> +#endif /* defined(CONFIG_PCI) */
>
> #if defined(CONFIG_POST)
> /*
> @@ -488,12 +542,12 @@ int is_pci_host(struct pci_controller *hose)
> */
> int post_hotkeys_pressed(void)
> {
> - return 0; /* No hotkeys supported */
> + return 0; /* No hotkeys supported */
> }
> #endif /* CONFIG_POST */
>
> #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
> -void ft_board_setup(void *blob, bd_t *bd)
> +void ft_board_setup(void *blob, bd_t * bd)
> {
> ft_cpu_setup(blob, bd);
>
> @@ -504,7 +558,7 @@ void ft_board_setup(void *blob, bd_t *bd)
> * Hardcoded flash setup:
> * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
> */
> -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *
> info) +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t
> * info) {
> if (banknum == 0) { /* non-CFI boot flash */
> info->portwidth = 1;
> diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
> index 0546cd7..d52cf99 100644
> --- a/board/netstal/hcu5/sdram.c
> +++ b/board/netstal/hcu5/sdram.c
> @@ -36,9 +36,11 @@
> #include <asm/mmu.h>
> #include <asm/cache.h>
> #include <ppc440.h>
> +#include <post.h>
>
> void hcu_led_set(u32 value);
> void dcbz_area(u32 start_address, u32 num_bytes);
> +void zero_all_memory(unsigned long start_address, unsigned long
> num_bytes);
>
> #define ECC_RAM 0x03267F0B
> #define NO_ECC_RAM 0x00267F0B
> @@ -48,6 +50,11 @@ void dcbz_area(u32 start_address, u32 num_bytes);
> #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
> /* disable caching on DDR2 */
>
> +/* PPC440EPx Erratum CHIP_11: End of memory range area restricted access.
> + * -> no access to last 256 Bytes!!!
> + */
> +#define NO_TOUCH_BYTES_AT_END 256
Please take a look at this define in sequoia.h:
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
Doesn't this work for you as well?
Cheers,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
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