[U-Boot] [PATCH v2] Add generic support for samsung s3c2440

C Nauman cnauman at diagraph.com
Tue Aug 24 20:18:55 CEST 2010


Minkyu,

- This patch adds generic support for the Samsung s3c2440 processor.
        Started from patch posted by Kevin Morfitt.
- v2 Changed struct members to lower case

Signed-off-by: Craig Nauman <cnauman at diagraph.com>
---
 arch/arm/cpu/arm920t/s3c24x0/speed.c            |   36 +-
 arch/arm/cpu/arm920t/s3c24x0/timer.c            |   23 +-
 arch/arm/cpu/arm920t/s3c24x0/usb.c              |   10 +-
 arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c         |   12 +-
 arch/arm/include/asm/arch-s3c24x0/s3c2440.h     |  163 ++++++
 arch/arm/include/asm/arch-s3c24x0/s3c24x0.h     |  672 
+++++++++++++----------
 arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h |    2 +
 board/mpl/vcma9/vcma9.c                         |   40 +-
 board/samsung/smdk2400/smdk2400.c               |   28 +-
 board/samsung/smdk2410/smdk2410.c               |   36 +-
 board/sbc2410x/sbc2410x.c                       |   44 +-
 board/trab/cmd_trab.c                           |   28 +-
 board/trab/rs485.c                              |   38 +-
 board/trab/trab.c                               |   66 ++--
 board/trab/trab_fkt.c                           |  142 +++---
 board/trab/tsc2000.c                            |   38 +-
 board/trab/tsc2000.h                            |   64 ++--
 board/trab/vfd.c                                |   86 ++--
 drivers/i2c/s3c24x0_i2c.c                       |  102 ++--
 drivers/mtd/nand/s3c2410_nand.c                 |    8 +-
 drivers/rtc/s3c24x0_rtc.c                       |   52 +-
 drivers/serial/serial_s3c24x0.c                 |   26 +-
 22 files changed, 993 insertions(+), 723 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-s3c24x0/s3c2440.h

diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c 
b/arch/arm/cpu/arm920t/s3c24x0/speed.c
index b13283a..836e60d 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/speed.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c
@@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg)
     ulong r, m, p, s;
 
     if (pllreg == MPLL)
-        r = readl(&clk_power->MPLLCON);
+        r = readl(&clk_power->mpllcon);
     else if (pllreg == UPLL)
-        r = readl(&clk_power->UPLLCON);
+        r = readl(&clk_power->upllcon);
     else
         hang();
 
@@ -64,7 +64,18 @@ static ulong get_PLLCLK(int pllreg)
     p = ((r & 0x003F0) >> 4) + 2;
     s = r & 0x3;
 
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
     return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
+#elif defined(CONFIG_S3C2440)
+    /* To avoid integer overflow, changed the calc order */
+    if (pllreg == MPLL)
+        return ( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
+    else
+        return ( m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
+#else
+#error "get_PLLCLK not implemented for CPU type"
+#endif
+       
 }
 
 /* return FCLK frequency */
@@ -77,8 +88,23 @@ ulong get_FCLK(void)
 ulong get_HCLK(void)
 {
     struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
-    return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+    return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
+#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+    switch (readl(&clk_power->clkdivn) & 0x6) {
+        case 0x0:
+        return get_FCLK();
+    case 0x2:
+        return get_FCLK()/2;
+    case 0x4:
+        return (readl(&clk_power->camdivn) & 0x200) ? get_FCLK()/8 : 
get_FCLK()/4;
+    case 0x6:
+        return (readl(&clk_power->camdivn) & 0x100) ? get_FCLK()/6 : 
get_FCLK()/3;
+    }
+    return 0;
+#else
+#error "get_HCLK not implemented for CPU type"
+#endif
 }
 
 /* return PCLK frequency */
@@ -86,7 +112,7 @@ ulong get_PCLK(void)
 {
     struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 
-    return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
+    return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
 }
 
 /* return UCLK frequency */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c 
b/arch/arm/cpu/arm920t/s3c24x0/timer.c
index 7d47354..84fa6f6 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void)
 {
     struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
 
-    return readl(&timers->TCNTO4) & 0xffff;
+    return readl(&timers->tcnto4) & 0xffff;
 }
 
 static ulong timestamp;
@@ -56,7 +56,7 @@ int timer_init(void)
 
     /* use PWM Timer 4 because it has no output */
     /* prescaler for Timer 4 is 16 */
-    writel(0x0f00, &timers->TCFG0);
+    writel(0x0f00, &timers->tcfg0);
     if (timer_load_val == 0) {
         /*
          * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
@@ -68,13 +68,13 @@ int timer_init(void)
     }
     /* load value for 10 ms timeout */
     lastdec = timer_load_val;
-    writel(timer_load_val, &timers->TCNTB4);
-    /* auto load, manual update of Timer 4 */
-    tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
-    writel(tmr, &timers->TCON);
-    /* auto load, start Timer 4 */
+    writel(timer_load_val, &timers->tcntb4);
+    /* auto load, manual update of timer 4 */
+    tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
+    writel(tmr, &timers->tcon);
+    /* auto load, start timer 4 */
     tmr = (tmr & ~0x0700000) | 0x0500000;
-    writel(tmr, &timers->TCON);
+    writel(tmr, &timers->tcon);
     timestamp = 0;
 
     return (0);
@@ -181,6 +181,7 @@ ulong get_tbclk(void)
     tbclk = timer_load_val * 100;
 #elif defined(CONFIG_SBC2410X) || \
       defined(CONFIG_SMDK2410) || \
+      defined(CONFIG_IJ3K2440) || \
       defined(CONFIG_VCMA9)
     tbclk = CONFIG_SYS_HZ;
 #else
@@ -206,13 +207,13 @@ void reset_cpu(ulong ignored)
     watchdog = s3c24x0_get_base_watchdog();
 
     /* Disable watchdog */
-    writel(0x0000, &watchdog->WTCON);
+    writel(0x0000, &watchdog->wtcon);
 
     /* Initialize watchdog timer count register */
-    writel(0x0001, &watchdog->WTCNT);
+    writel(0x0001, &watchdog->wtcnt);
 
     /* Enable watchdog timer; assert reset at timer timeout */
-    writel(0x0021, &watchdog->WTCON);
+    writel(0x0021, &watchdog->wtcon);
 
     while (1)
         /* loop forever and wait for reset to happen */;
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c 
b/arch/arm/cpu/arm920t/s3c24x0/usb.c
index e468ed0..226a3f6 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/usb.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/usb.c
@@ -39,14 +39,14 @@ int usb_cpu_init(void)
      * Set the 48 MHz UPLL clocking. Values are taken from
      * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
      */
-    writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+    writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
     /* 1 = use pads related USB for USB host */
-    writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
+    writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
 
     /*
      * Enable USB host clock.
      */
-    writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+    writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 
     return 0;
 }
@@ -55,14 +55,14 @@ int usb_cpu_stop(void)
 {
     struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
     /* may not want to do this */
-    writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+    writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
     return 0;
 }
 
 int usb_cpu_init_fail(void)
 {
     struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-    writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+    writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
     return 0;
 }
 
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c 
b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
index 5aa8d64..ccc9738 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -1666,13 +1666,13 @@ int usb_lowlevel_init(void)
      * Set the 48 MHz UPLL clocking. Values are taken from
      * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
      */
-    clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
-    gpio->MISCCR |= 0x8;    /* 1 = use pads related USB for USB host */
+    clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
+    gpio->misccr |= 0x8;    /* 1 = use pads related USB for USB host */
 
     /*
      * Enable USB host clock.
      */
-    clk_power->CLKCON |= (1 << 4);
+    clk_power->clkcon |= (1 << 4);
 
     memset(&gohci, 0, sizeof(struct ohci));
     memset(&urb_priv, 0, sizeof(struct urb_priv));
@@ -1709,7 +1709,7 @@ int usb_lowlevel_init(void)
     if (hc_reset(&gohci) < 0) {
         hc_release_ohci(&gohci);
         /* Initialization failed */
-        clk_power->CLKCON &= ~(1 << 4);
+        clk_power->clkcon &= ~(1 << 4);
         return -1;
     }
 
@@ -1722,7 +1722,7 @@ int usb_lowlevel_init(void)
         err("can't start usb-%s", gohci.slot_name);
         hc_release_ohci(&gohci);
         /* Initialization failed */
-        clk_power->CLKCON &= ~(1 << 4);
+        clk_power->clkcon &= ~(1 << 4);
         return -1;
     }
 #ifdef    DEBUG
@@ -1748,7 +1748,7 @@ int usb_lowlevel_stop(void)
     /* call hc_release_ohci() here ? */
     hc_reset(&gohci);
     /* may not want to do this */
-    clk_power->CLKCON &= ~(1 << 4);
+    clk_power->clkcon &= ~(1 << 4);
     return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h 
b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
new file mode 100644
index 0000000..7e4518e
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
@@ -0,0 +1,163 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller at elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME        : s3c2440.h
+ * Version  : 31.3.2003
+ *
+ * Based on S3C2440 User's manual Rev x.x
+ ************************************************/
+
+#ifndef __S3C2440_H__
+#define __S3C2440_H__
+
+#define S3C24X0_UART_CHANNELS    3
+#define S3C24X0_SPI_CHANNELS    2
+
+/* S3C2440 only supports 512 Byte HW ECC */
+#define S3C2440_ECCSIZE        512
+#define S3C2440_ECCBYTES    3
+
+enum s3c24x0_uarts_nr {
+    S3C24X0_UART0,
+    S3C24X0_UART1,
+    S3C24X0_UART2
+};
+
+/* S3C2440 device base addresses */
+#define S3C24X0_MEMCTL_BASE        0x48000000
+#define S3C24X0_USB_HOST_BASE        0x49000000
+#define S3C24X0_INTERRUPT_BASE        0x4A000000
+#define S3C24X0_DMA_BASE        0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE    0x4C000000
+#define S3C24X0_LCD_BASE        0x4D000000
+#define S3C2440_NAND_BASE        0x4E000000
+#define S3C24X0_UART_BASE        0x50000000
+#define S3C24X0_TIMER_BASE        0x51000000
+#define S3C24X0_USB_DEVICE_BASE        0x52000140
+#define S3C24X0_WATCHDOG_BASE        0x53000000
+#define S3C24X0_I2C_BASE        0x54000000
+#define S3C24X0_I2S_BASE        0x55000000
+#define S3C24X0_GPIO_BASE        0x56000000
+#define S3C24X0_RTC_BASE        0x57000000
+#define S3C2440_ADC_BASE        0x58000000
+#define S3C24X0_SPI_BASE        0x59000000
+#define S3C2440_SDI_BASE        0x5A000000
+
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+    return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+    return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+    return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+    return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+
+static inline struct s3c24x0_clock_power 
*s3c24x0_get_base_clock_power(void)
+{
+    return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+    return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+
+static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
+{
+    return (struct s3c2440_nand *)S3C2440_NAND_BASE;
+}
+
+static inline struct s3c24x0_uart
+    *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+    return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+    return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+    return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+    return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+    return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+    return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+    return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+    return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+
+static inline struct s3c2440_adc *s3c2440_get_base_adc(void)
+{
+    return (struct s3c2440_adc *)S3C2440_ADC_BASE;
+}
+
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+    return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
+{
+    return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
+}
+
+#endif /*__S3C2440_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h 
b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index 15f53dd..d1b96cc 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -33,12 +33,12 @@
 
 /* Memory controller (see manual chapter 5) */
 struct s3c24x0_memctl {
-    u32    BWSCON;
-    u32    BANKCON[8];
-    u32    REFRESH;
-    u32    BANKSIZE;
-    u32    MRSRB6;
-    u32    MRSRB7;
+    u32    bwscon;
+    u32    bankcon[8];
+    u32    refresh;
+    u32    banksize;
+    u32    mrsrb6;
+    u32    mrsrb7;
 };
 
 
@@ -72,40 +72,38 @@ struct s3c24x0_usb_host {
 
 /* INTERRUPT (see manual chapter 14) */
 struct s3c24x0_interrupt {
-    u32    SRCPND;
-    u32    INTMOD;
-    u32    INTMSK;
-    u32    PRIORITY;
-    u32    INTPND;
-    u32    INTOFFSET;
-#ifdef CONFIG_S3C2410
-    u32    SUBSRCPND;
-    u32    INTSUBMSK;
+    u32    srcpnd;
+    u32    intmod;
+    u32    intmsk;
+    u32    priority;
+    u32    intpnd;
+    u32    intoffset;
+#if defined (CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+    u32    subsrcpnd;
+    u32    intsubmsk;
 #endif
 };
 
 
 /* DMAS (see manual chapter 8) */
 struct s3c24x0_dma {
-    u32    DISRC;
-#ifdef CONFIG_S3C2410
-    u32    DISRCC;
+    u32    disrc;
+#if defined (CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+    u32    disrcc;
 #endif
-    u32    DIDST;
-#ifdef CONFIG_S3C2410
-    u32    DIDSTC;
+    u32    didst;
+#if defined (CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+    u32    didstc;
 #endif
-    u32    DCON;
-    u32    DSTAT;
-    u32    DCSRC;
-    u32    DCDST;
-    u32    DMASKTRIG;
-#ifdef CONFIG_S3C2400
+    u32    dcon;
+    u32    dstat;
+    u32    dcsrc;
+    u32    dcdst;
+    u32    dmasktrig;
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
+        || defined(CONFIG_S3C2440)
     u32    res[1];
 #endif
-#ifdef CONFIG_S3C2410
-    u32    res[7];
-#endif
 };
 
 struct s3c24x0_dmas {
@@ -116,90 +114,111 @@ struct s3c24x0_dmas {
 /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
 /*                          (see S3C2410 manual chapter 7) */
 struct s3c24x0_clock_power {
-    u32    LOCKTIME;
-    u32    MPLLCON;
-    u32    UPLLCON;
-    u32    CLKCON;
-    u32    CLKSLOW;
-    u32    CLKDIVN;
+    u32    locktime;
+    u32    mpllcon;
+    u32    upllcon;
+    u32    clkcon;
+    u32    clkslow;
+    u32    clkdivn;
+#if defined(CONFIG_S3C2440)
+    u32    camdivn;
+#endif
 };
 
 
 /* LCD CONTROLLER (see manual chapter 15) */
 struct s3c24x0_lcd {
-    u32    LCDCON1;
-    u32    LCDCON2;
-    u32    LCDCON3;
-    u32    LCDCON4;
-    u32    LCDCON5;
-    u32    LCDSADDR1;
-    u32    LCDSADDR2;
-    u32    LCDSADDR3;
-    u32    REDLUT;
-    u32    GREENLUT;
-    u32    BLUELUT;
+    u32    lcdcon1;
+    u32    lcdcon2;
+    u32    lcdcon3;
+    u32    lcdcon4;
+    u32    lcdcon5;
+    u32    lcdsaddr1;
+    u32    lcdsaddr2;
+    u32    lcdsaddr3;
+    u32    redlut;
+    u32    greenlut;
+    u32    bluelut;
     u32    res[8];
-    u32    DITHMODE;
-    u32    TPAL;
-#ifdef CONFIG_S3C2410
-    u32    LCDINTPND;
-    u32    LCDSRCPND;
-    u32    LCDINTMSK;
-    u32    LPCSEL;
+    u32    dithmode;
+    u32    tpal;
+#if defined (CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+    u32    lcdintpnd;
+    u32    lcdsrcpnd;
+    u32    lcdintmsk;
+    u32    lpcsel;
 #endif
 };
 
 
+#ifdef CONFIG_S3C2410
 /* NAND FLASH (see S3C2410 manual chapter 6) */
 struct s3c2410_nand {
-    u32    NFCONF;
-    u32    NFCMD;
-    u32    NFADDR;
-    u32    NFDATA;
-    u32    NFSTAT;
-    u32    NFECC;
+    u32    nfconf;
+    u32    nfcmd;
+    u32    nfaddr;
+    u32    nfdata;
+    u32    nfstat;
+    u32    nfecc;
+};
+#endif
+#ifdef CONFIG_S3C2440
+/* NAND FLASH (see S3C2440 manual chapter 6) */
+struct s3c2440_nand {
+    u32    nfconf;
+    u32    nfcont;
+    u32    nfcmd;
+    u32    nfaddr;
+    u32    nfdata;
+    u32    nfeccd0;
+    u32    nfeccd1;
+    u32    nfeccd;
+    u32    nfstat;
+    u32    nfstat0;
+    u32    nfstat1;
 };
+#endif
 
 
 /* UART (see manual chapter 11) */
 struct s3c24x0_uart {
-    u32    ULCON;
-    u32    UCON;
-    u32    UFCON;
-    u32    UMCON;
-    u32    UTRSTAT;
-    u32    UERSTAT;
-    u32    UFSTAT;
-    u32    UMSTAT;
+    u32    ulcon;
+    u32    ucon;
+    u32    ufcon;
+    u32    umcon;
+    u32    utrstat;
+    u32    uerstat;
+    u32    ufstat;
+    u32    umstat;
 #ifdef __BIG_ENDIAN
     u8    res1[3];
-    u8    UTXH;
+    u8    utxh;
     u8    res2[3];
-    u8    URXH;
+    u8    urxh;
 #else /* Little Endian */
-    u8    UTXH;
+    u8    utxh;
     u8    res1[3];
-    u8    URXH;
+    u8    urxh;
     u8    res2[3];
 #endif
-    u32    UBRDIV;
+    u32    ubrdiv;
 };
 
 
 /* PWM TIMER (see manual chapter 10) */
 struct s3c24x0_timer {
-    u32    TCNTB;
-    u32    TCMPB;
-    u32    TCNTO;
+    u32    tcntb;
+    u32    tcmpb;
+    u32    tcnto;
 };
 
 struct s3c24x0_timers {
-    u32    TCFG0;
-    u32    TCFG1;
-    u32    TCON;
+    u32    tcfg0;
+    u32    tcfg1;
+    u32    tcon;
     struct s3c24x0_timer    ch[4];
-    u32    TCNTB4;
-    u32    TCNTO4;
+    u32    tcntb4;
+    u32    tcnto4;
 };
 
 
@@ -207,9 +226,9 @@ struct s3c24x0_timers {
 struct s3c24x0_usb_dev_fifos {
 #ifdef __BIG_ENDIAN
     u8    res[3];
-    u8    EP_FIFO_REG;
+    u8    ep_fifo_reg;
 #else /*  little endian */
-    u8    EP_FIFO_REG;
+    u8    ep_fifo_reg;
     u8    res[3];
 #endif
 };
@@ -217,29 +236,29 @@ struct s3c24x0_usb_dev_fifos {
 struct s3c24x0_usb_dev_dmas {
 #ifdef __BIG_ENDIAN
     u8    res1[3];
-    u8    EP_DMA_CON;
+    u8    ep_dma_con;
     u8    res2[3];
-    u8    EP_DMA_UNIT;
+    u8    ep_dma_unit;
     u8    res3[3];
-    u8    EP_DMA_FIFO;
+    u8    ep_dma_fifo;
     u8    res4[3];
-    u8    EP_DMA_TTC_L;
+    u8    ep_dma_ttc_l;
     u8    res5[3];
-    u8    EP_DMA_TTC_M;
+    u8    ep_dma_ttc_m;
     u8    res6[3];
-    u8    EP_DMA_TTC_H;
+    u8    ep_dma_ttc_h;
 #else /*  little endian */
-    u8    EP_DMA_CON;
+    u8    ep_dma_con;
     u8    res1[3];
-    u8    EP_DMA_UNIT;
+    u8    ep_dma_unit;
     u8    res2[3];
-    u8    EP_DMA_FIFO;
+    u8    ep_dma_fifo;
     u8    res3[3];
-    u8    EP_DMA_TTC_L;
+    u8    ep_dma_ttc_l;
     u8    res4[3];
-    u8    EP_DMA_TTC_M;
+    u8    ep_dma_ttc_m;
     u8    res5[3];
-    u8    EP_DMA_TTC_H;
+    u8    ep_dma_ttc_h;
     u8    res6[3];
 #endif
 };
@@ -247,69 +266,69 @@ struct s3c24x0_usb_dev_dmas {
 struct s3c24x0_usb_device {
 #ifdef __BIG_ENDIAN
     u8    res1[3];
-    u8    FUNC_ADDR_REG;
+    u8    func_addr_reg;
     u8    res2[3];
-    u8    PWR_REG;
+    u8    pwr_reg;
     u8    res3[3];
-    u8    EP_INT_REG;
+    u8    ep_int_reg;
     u8    res4[15];
-    u8    USB_INT_REG;
+    u8    usb_int_reg;
     u8    res5[3];
-    u8    EP_INT_EN_REG;
+    u8    ep_int_en_reg;
     u8    res6[15];
-    u8    USB_INT_EN_REG;
+    u8    usb_int_en_reg;
     u8    res7[3];
-    u8    FRAME_NUM1_REG;
+    u8    frame_num1_reg;
     u8    res8[3];
-    u8    FRAME_NUM2_REG;
+    u8    frame_num2_reg;
     u8    res9[3];
-    u8    INDEX_REG;
+    u8    index_reg;
     u8    res10[7];
-    u8    MAXP_REG;
+    u8    maxp_reg;
     u8    res11[3];
-    u8    EP0_CSR_IN_CSR1_REG;
+    u8    ep0_csr_in_csr1_reg;
     u8    res12[3];
-    u8    IN_CSR2_REG;
+    u8    in_csr2_reg;
     u8    res13[7];
-    u8    OUT_CSR1_REG;
+    u8    out_csr1_reg;
     u8    res14[3];
-    u8    OUT_CSR2_REG;
+    u8    out_csr2_reg;
     u8    res15[3];
-    u8    OUT_FIFO_CNT1_REG;
+    u8    out_fifo_cnt1_reg;
     u8    res16[3];
-    u8    OUT_FIFO_CNT2_REG;
+    u8    out_fifo_cnt2_reg;
 #else /*  little endian */
-    u8    FUNC_ADDR_REG;
+    u8    func_addr_reg;
     u8    res1[3];
-    u8    PWR_REG;
+    u8    pwr_reg;
     u8    res2[3];
-    u8    EP_INT_REG;
+    u8    ep_int_reg;
     u8    res3[15];
-    u8    USB_INT_REG;
+    u8    usb_int_reg;
     u8    res4[3];
-    u8    EP_INT_EN_REG;
+    u8    ep_int_en_reg;
     u8    res5[15];
-    u8    USB_INT_EN_REG;
+    u8    usb_int_en_reg;
     u8    res6[3];
-    u8    FRAME_NUM1_REG;
+    u8    frame_num1_reg;
     u8    res7[3];
-    u8    FRAME_NUM2_REG;
+    u8    frame_num2_reg;
     u8    res8[3];
-    u8    INDEX_REG;
+    u8    index_reg;
     u8    res9[7];
-    u8    MAXP_REG;
+    u8    maxp_reg;
     u8    res10[7];
-    u8    EP0_CSR_IN_CSR1_REG;
+    u8    ep0_csr_in_csr1_reg;
     u8    res11[3];
-    u8    IN_CSR2_REG;
+    u8    in_csr2_reg;
     u8    res12[3];
-    u8    OUT_CSR1_REG;
+    u8    out_csr1_reg;
     u8    res13[7];
-    u8    OUT_CSR2_REG;
+    u8    out_csr2_reg;
     u8    res14[3];
-    u8    OUT_FIFO_CNT1_REG;
+    u8    out_fifo_cnt1_reg;
     u8    res15[3];
-    u8    OUT_FIFO_CNT2_REG;
+    u8    out_fifo_cnt2_reg;
     u8    res16[3];
 #endif /*  __BIG_ENDIAN */
     struct s3c24x0_usb_dev_fifos    fifo[5];
@@ -319,18 +338,18 @@ struct s3c24x0_usb_device {
 
 /* WATCH DOG TIMER (see manual chapter 18) */
 struct s3c24x0_watchdog {
-    u32    WTCON;
-    u32    WTDAT;
-    u32    WTCNT;
+    u32    wtcon;
+    u32    wtdat;
+    u32    wtcnt;
 };
 
 
 /* IIC (see manual chapter 20) */
 struct s3c24x0_i2c {
-    u32    IICCON;
-    u32    IICSTAT;
-    u32    IICADD;
-    u32    IICDS;
+    u32    iiccon;
+    u32    iicstat;
+    u32    iicadd;
+    u32    iicds;
 };
 
 
@@ -338,25 +357,25 @@ struct s3c24x0_i2c {
 struct s3c24x0_i2s {
 #ifdef __BIG_ENDIAN
     u16    res1;
-    u16    IISCON;
+    u16    iiscon;
     u16    res2;
-    u16    IISMOD;
+    u16    iismod;
     u16    res3;
-    u16    IISPSR;
+    u16    iispsr;
     u16    res4;
-    u16    IISFCON;
+    u16    iisfcon;
     u16    res5;
-    u16    IISFIFO;
+    u16    iisfifo;
 #else /*  little endian */
-    u16    IISCON;
+    u16    iiscon;
     u16    res1;
-    u16    IISMOD;
+    u16    iismod;
     u16    res2;
-    u16    IISPSR;
+    u16    iispsr;
     u16    res3;
-    u16    IISFCON;
+    u16    iisfcon;
     u16    res4;
-    u16    IISFIFO;
+    u16    iisfifo;
     u16    res5;
 #endif
 };
@@ -365,87 +384,146 @@ struct s3c24x0_i2s {
 /* I/O PORT (see manual chapter 9) */
 struct s3c24x0_gpio {
 #ifdef CONFIG_S3C2400
-    u32    PACON;
-    u32    PADAT;
+    u32    pacon;
+    u32    padat;
 
-    u32    PBCON;
-    u32    PBDAT;
-    u32    PBUP;
+    u32    pbcon;
+    u32    pbdat;
+    u32    pbup;
 
-    u32    PCCON;
-    u32    PCDAT;
-    u32    PCUP;
+    u32    pccon;
+    u32    pcdat;
+    u32    pcup;
 
-    u32    PDCON;
-    u32    PDDAT;
-    u32    PDUP;
+    u32    pdcon;
+    u32    pddat;
+    u32    pdup;
 
-    u32    PECON;
-    u32    PEDAT;
-    u32    PEUP;
+    u32    pecon;
+    u32    pedat;
+    u32    peup;
 
-    u32    PFCON;
-    u32    PFDAT;
-    u32    PFUP;
+    u32    pfcon;
+    u32    pfdat;
+    u32    pfup;
 
-    u32    PGCON;
-    u32    PGDAT;
-    u32    PGUP;
+    u32    pgcon;
+    u32    pgdat;
+    u32    pgup;
 
-    u32    OPENCR;
+    u32    opencr;
 
-    u32    MISCCR;
-    u32    EXTINT;
+    u32    misccr;
+    u32    extint;
 #endif
 #ifdef CONFIG_S3C2410
-    u32    GPACON;
-    u32    GPADAT;
+    u32    gpacon;
+    u32    gpadat;
+    u32    res1[2];
+    u32    gpbcon;
+    u32    gpbdat;
+    u32    gpbup;
+    u32    res2;
+    u32    gpccon;
+    u32    gpcdat;
+    u32    gpcup;
+    u32    res3;
+    u32    gpdcon;
+    u32    gpddat;
+    u32    gpdup;
+    u32    res4;
+    u32    gpecon;
+    u32    gpedat;
+    u32    gpeup;
+    u32    res5;
+    u32    gpfcon;
+    u32    gpfdat;
+    u32    gpfup;
+    u32    res6;
+    u32    gpgcon;
+    u32    gpgdat;
+    u32    gpgup;
+    u32    res7;
+    u32    gphcon;
+    u32    gphdat;
+    u32    gphup;
+    u32    res8;
+
+    u32    misccr;
+    u32    dclkcon;
+    u32    extint0;
+    u32    extint1;
+    u32    extint2;
+    u32    eintflt0;
+    u32    eintflt1;
+    u32    eintflt2;
+    u32    eintflt3;
+    u32    eintmask;
+    u32    eintpend;
+    u32    gstatus0;
+    u32    gstatus1;
+    u32    gstatus2;
+    u32    gstatus3;
+    u32    gstatus4;
+#endif
+#if defined(CONFIG_S3C2440)
+    u32    gpacon;
+    u32    gpadat;
     u32    res1[2];
-    u32    GPBCON;
-    u32    GPBDAT;
-    u32    GPBUP;
+    u32    gpbcon;
+    u32    gpbdat;
+    u32    gpbup;
     u32    res2;
-    u32    GPCCON;
-    u32    GPCDAT;
-    u32    GPCUP;
+    u32    gpccon;
+    u32    gpcdat;
+    u32    gpcup;
     u32    res3;
-    u32    GPDCON;
-    u32    GPDDAT;
-    u32    GPDUP;
+    u32    gpdcon;
+    u32    gpddat;
+    u32    gpdup;
     u32    res4;
-    u32    GPECON;
-    u32    GPEDAT;
-    u32    GPEUP;
+    u32    gpecon;
+    u32    gpedat;
+    u32    gpeup;
     u32    res5;
-    u32    GPFCON;
-    u32    GPFDAT;
-    u32    GPFUP;
+    u32    gpfcon;
+    u32    gpfdat;
+    u32    gpfup;
     u32    res6;
-    u32    GPGCON;
-    u32    GPGDAT;
-    u32    GPGUP;
+    u32    gpgcon;
+    u32    gpgdat;
+    u32    gpgup;
     u32    res7;
-    u32    GPHCON;
-    u32    GPHDAT;
-    u32    GPHUP;
+    u32    gphcon;
+    u32    gphdat;
+    u32    gphup;
     u32    res8;
 
-    u32    MISCCR;
-    u32    DCLKCON;
-    u32    EXTINT0;
-    u32    EXTINT1;
-    u32    EXTINT2;
-    u32    EINTFLT0;
-    u32    EINTFLT1;
-    u32    EINTFLT2;
-    u32    EINTFLT3;
-    u32    EINTMASK;
-    u32    EINTPEND;
-    u32    GSTATUS0;
-    u32    GSTATUS1;
-    u32    GSTATUS2;
-    u32    GSTATUS3;
-    u32    GSTATUS4;
+    u32    misccr;
+    u32    dclkcon;
+    u32    extint0;
+    u32    extint1;
+    u32    extint2;
+    u32    eintflt0;
+    u32    eintflt1;
+    u32    eintflt2;
+    u32    eintflt3;
+    u32    eintmask;
+    u32    eintpend;
+    u32    gstatus0;
+    u32    gstatus1;
+    u32    gstatus2;
+    u32    gstatus3;
+    u32    gstatus4;
+
+    u32    res9;
+    u32    dsc0;
+    u32    dsc1;
+    u32    mslcon;
+    u32    gpjcon;
+    u32    gpjdat;
+    u32    gpjup;
+    u32    res10;
 #endif
 };
 
@@ -454,74 +532,74 @@ struct s3c24x0_gpio {
 struct s3c24x0_rtc {
 #ifdef __BIG_ENDIAN
     u8    res1[67];
-    u8    RTCCON;
+    u8    rtccon;
     u8    res2[3];
-    u8    TICNT;
+    u8    ticnt;
     u8    res3[11];
-    u8    RTCALM;
+    u8    rtcalm;
     u8    res4[3];
-    u8    ALMSEC;
+    u8    almsec;
     u8    res5[3];
-    u8    ALMMIN;
+    u8    almmin;
     u8    res6[3];
-    u8    ALMHOUR;
+    u8    almhour;
     u8    res7[3];
-    u8    ALMDATE;
+    u8    almdate;
     u8    res8[3];
-    u8    ALMMON;
+    u8    almmon;
     u8    res9[3];
-    u8    ALMYEAR;
+    u8    almyear;
     u8    res10[3];
-    u8    RTCRST;
+    u8    rtcrst;
     u8    res11[3];
-    u8    BCDSEC;
+    u8    bcdsec;
     u8    res12[3];
-    u8    BCDMIN;
+    u8    bcdmin;
     u8    res13[3];
-    u8    BCDHOUR;
+    u8    bcdhour;
     u8    res14[3];
-    u8    BCDDATE;
+    u8    bcddate;
     u8    res15[3];
-    u8    BCDDAY;
+    u8    bcdday;
     u8    res16[3];
-    u8    BCDMON;
+    u8    bcdmon;
     u8    res17[3];
-    u8    BCDYEAR;
+    u8    bcdyear;
 #else /*  little endian */
     u8    res0[64];
-    u8    RTCCON;
+    u8    rtccon;
     u8    res1[3];
-    u8    TICNT;
+    u8    ticnt;
     u8    res2[11];
-    u8    RTCALM;
+    u8    rtcalm;
     u8    res3[3];
-    u8    ALMSEC;
+    u8    almsec;
     u8    res4[3];
-    u8    ALMMIN;
+    u8    almmin;
     u8    res5[3];
-    u8    ALMHOUR;
+    u8    almhour;
     u8    res6[3];
-    u8    ALMDATE;
+    u8    almdate;
     u8    res7[3];
-    u8    ALMMON;
+    u8    almmon;
     u8    res8[3];
-    u8    ALMYEAR;
+    u8    almyear;
     u8    res9[3];
-    u8    RTCRST;
+    u8    rtcrst;
     u8    res10[3];
-    u8    BCDSEC;
+    u8    bcdsec;
     u8    res11[3];
-    u8    BCDMIN;
+    u8    bcdmin;
     u8    res12[3];
-    u8    BCDHOUR;
+    u8    bcdhour;
     u8    res13[3];
-    u8    BCDDATE;
+    u8    bcddate;
     u8    res14[3];
-    u8    BCDDAY;
+    u8    bcdday;
     u8    res15[3];
-    u8    BCDMON;
+    u8    bcdmon;
     u8    res16[3];
-    u8    BCDYEAR;
+    u8    bcdyear;
     u8    res17[3];
 #endif
 };
@@ -529,34 +607,34 @@ struct s3c24x0_rtc {
 
 /* ADC (see manual chapter 16) */
 struct s3c2400_adc {
-    u32    ADCCON;
-    u32    ADCDAT;
+    u32    adccon;
+    u32    adcdat;
 };
 
 
 /* ADC (see manual chapter 16) */
 struct s3c2410_adc {
-    u32    ADCCON;
-    u32    ADCTSC;
-    u32    ADCDLY;
-    u32    ADCDAT0;
-    u32    ADCDAT1;
+    u32    adccon;
+    u32    adctsc;
+    u32    adcdly;
+    u32    adcdat0;
+    u32    adcdat1;
 };
 
 
 /* SPI (see manual chapter 22) */
 struct s3c24x0_spi_channel {
-    u8    SPCON;
+    u8    spcon;
     u8    res1[3];
-    u8    SPSTA;
+    u8    spsta;
     u8    res2[3];
-    u8    SPPIN;
+    u8    sppin;
     u8    res3[3];
-    u8    SPPRE;
+    u8    sppre;
     u8    res4[3];
-    u8    SPTDAT;
+    u8    sptdat;
     u8    res5[3];
-    u8    SPRDAT;
+    u8    sprdat;
     u8    res6[3];
     u8    res7[16];
 };
@@ -570,53 +648,53 @@ struct s3c24x0_spi {
 struct s3c2400_mmc {
 #ifdef __BIG_ENDIAN
     u8    res1[3];
-    u8    MMCON;
+    u8    mmcon;
     u8    res2[3];
-    u8    MMCRR;
+    u8    mmcrr;
     u8    res3[3];
-    u8    MMFCON;
+    u8    mmfcon;
     u8    res4[3];
-    u8    MMSTA;
+    u8    mmsta;
     u16    res5;
-    u16    MMFSTA;
+    u16    mmfsta;
     u8    res6[3];
-    u8    MMPRE;
+    u8    mmpre;
     u16    res7;
-    u16    MMLEN;
+    u16    mmlen;
     u8    res8[3];
-    u8    MMCR7;
-    u32    MMRSP[4];
+    u8    mmcr7;
+    u32    mmrsp[4];
     u8    res9[3];
-    u8    MMCMD0;
-    u32    MMCMD1;
+    u8    mmcmd0;
+    u32    mmcmd1;
     u16    res10;
-    u16    MMCR16;
+    u16    mmcr16;
     u8    res11[3];
-    u8    MMDAT;
+    u8    mmdat;
 #else
-    u8    MMCON;
+    u8    mmcon;
     u8    res1[3];
-    u8    MMCRR;
+    u8    mmcrr;
     u8    res2[3];
-    u8    MMFCON;
+    u8    mmfcon;
     u8    res3[3];
-    u8    MMSTA;
+    u8    mmsta;
     u8    res4[3];
-    u16    MMFSTA;
+    u16    mmfsta;
     u16    res5;
-    u8    MMPRE;
+    u8    mmpre;
     u8    res6[3];
-    u16    MMLEN;
+    u16    mmlen;
     u16    res7;
-    u8    MMCR7;
+    u8    mmcr7;
     u8    res8[3];
-    u32    MMRSP[4];
-    u8    MMCMD0;
+    u32    mmrsp[4];
+    u8    mmcmd0;
     u8    res9[3];
-    u32    MMCMD1;
-    u16    MMCR16;
+    u32    mmcmd1;
+    u16    mmcr16;
     u16    res10;
-    u8    MMDAT;
+    u8    mmdat;
     u8    res11[3];
 #endif
 };
@@ -624,29 +702,29 @@ struct s3c2400_mmc {
 
 /* SD INTERFACE (see S3C2410 manual chapter 19) */
 struct s3c2410_sdi {
-    u32    SDICON;
-    u32    SDIPRE;
-    u32    SDICARG;
-    u32    SDICCON;
-    u32    SDICSTA;
-    u32    SDIRSP0;
-    u32    SDIRSP1;
-    u32    SDIRSP2;
-    u32    SDIRSP3;
-    u32    SDIDTIMER;
-    u32    SDIBSIZE;
-    u32    SDIDCON;
-    u32    SDIDCNT;
-    u32    SDIDSTA;
-    u32    SDIFSTA;
+    u32    sdicon;
+    u32    sdipre;
+    u32    sdicarg;
+    u32    sdiccon;
+    u32    sdicsta;
+    u32    sdirsp0;
+    u32    sdirsp1;
+    u32    sdirsp2;
+    u32    sdirsp3;
+    u32    sdidtimer;
+    u32    sdibsize;
+    u32    sdidcon;
+    u32    sdidcnt;
+    u32    sdidsta;
+    u32    sdifsta;
 #ifdef __BIG_ENDIAN
     u8    res[3];
-    u8    SDIDAT;
+    u8    sdidat;
 #else
-    u8    SDIDAT;
+    u8    sdidat;
     u8    res[3];
 #endif
-    u32    SDIIMSK;
+    u32    sdiimsk;
 };
 
 #endif /*__S3C24X0_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h 
b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
index c37d4a1..54184c4 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
@@ -22,6 +22,8 @@
     #include <asm/arch/s3c2400.h>
 #elif defined CONFIG_S3C2410
     #include <asm/arch/s3c2410.h>
+#elif defined CONFIG_S3C2440
+    #include <asm/arch/s3c2440.h>
 #else
     #error Please define the s3c24x0 cpu type
 #endif
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index eaeec82..36f1939 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -78,42 +78,42 @@ int board_init(void)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     /* to reduce PLL lock time, adjust the LOCKTIME register */
-    clk_power->LOCKTIME = 0xFFFFFF;
+    clk_power->locktime = 0xFFFFFF;
 
     /* configure MPLL */
-    clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+    clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
     /* some delay between MPLL and UPLL */
     delay (4000);
 
     /* configure UPLL */
-    clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+    clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
     /* some delay between MPLL and UPLL */
     delay (8000);
 
     /* set up the I/O ports */
-    gpio->GPACON = 0x007FFFFF;
-    gpio->GPBCON = 0x002AAAAA;
-    gpio->GPBUP = 0x000002BF;
-    gpio->GPCCON = 0xAAAAAAAA;
-    gpio->GPCUP = 0x0000FFFF;
-    gpio->GPDCON = 0xAAAAAAAA;
-    gpio->GPDUP = 0x0000FFFF;
-    gpio->GPECON = 0xAAAAAAAA;
-    gpio->GPEUP = 0x000037F7;
-    gpio->GPFCON = 0x00000000;
-    gpio->GPFUP = 0x00000000;
-    gpio->GPGCON = 0xFFEAFF5A;
-    gpio->GPGUP = 0x0000F0DC;
-    gpio->GPHCON = 0x0028AAAA;
-    gpio->GPHUP = 0x00000656;
+    gpio->gpacon = 0x007FFFFF;
+    gpio->gpbcon = 0x002AAAAA;
+    gpio->gpbup = 0x000002BF;
+    gpio->gpccon = 0xAAAAAAAA;
+    gpio->gpcup = 0x0000FFFF;
+    gpio->gpdcon = 0xAAAAAAAA;
+    gpio->gpdup = 0x0000FFFF;
+    gpio->gpecon = 0xAAAAAAAA;
+    gpio->gpeup = 0x000037F7;
+    gpio->gpfcon = 0x00000000;
+    gpio->gpfup = 0x00000000;
+    gpio->gpgcon = 0xFFEAFF5A;
+    gpio->gpgup = 0x0000F0DC;
+    gpio->gphcon = 0x0028AAAA;
+    gpio->gphup = 0x00000656;
 
     /* setup correct IRQ modes for NIC */
-    gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge 
mode */
+    gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); /* rising edge 
mode */
 
     /* select USB port 2 to be host or device (fix to host for now) */
-    gpio->MISCCR |= 0x08;
+    gpio->misccr |= 0x08;
 
     /* init serial */
     gd->baudrate = CONFIG_BAUDRATE;
diff --git a/board/samsung/smdk2400/smdk2400.c 
b/board/samsung/smdk2400/smdk2400.c
index 1294d3f..05f5910 100644
--- a/board/samsung/smdk2400/smdk2400.c
+++ b/board/samsung/smdk2400/smdk2400.c
@@ -52,30 +52,30 @@ int board_init (void)
 
     /* memory and cpu-speed are setup before relocation */
     /* change the clock to be 50 MHz 1:1:1 */
-    clk_power->MPLLCON = 0x5c042;
-    clk_power->CLKDIVN = 0;
+    clk_power->mpllcon = 0x5c042;
+    clk_power->clkdivn = 0;
     /* set up the I/O ports */
-    gpio->PACON = 0x3ffff;
-    gpio->PBCON = 0xaaaaaaaa;
-    gpio->PBUP = 0xffff;
-    gpio->PECON = 0x0;
-    gpio->PEUP = 0x0;
+    gpio->pacon = 0x3ffff;
+    gpio->pbcon = 0xaaaaaaaa;
+    gpio->pbup = 0xffff;
+    gpio->pecon = 0x0;
+    gpio->peup = 0x0;
 #ifdef CONFIG_HWFLOW
     /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
     /*   10,   10,   00,   00,    10,   00,    10 */
-    gpio->PFCON=0xa22;
+    gpio->pfcon=0xa22;
     /* Disable pull-up on Rx, Tx, CTS and RTS pins */
-    gpio->PFUP=0x35;
+    gpio->pfup=0x35;
 #else
     /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
     /*   00,   00,   00,   00,    10,   00,    10 */
-    gpio->PFCON = 0x22;
+    gpio->pfcon = 0x22;
     /* Disable pull-up on Rx and Tx pins */
-    gpio->PFUP = 0x5;
+    gpio->pfup = 0x5;
 #endif    /* CONFIG_HWFLOW */
-    gpio->PGCON = 0x0;
-    gpio->PGUP = 0x0;
-    gpio->OPENCR = 0x0;
+    gpio->pgcon = 0x0;
+    gpio->pgup = 0x0;
+    gpio->opencr = 0x0;
 
     /* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
     gd->bd->bi_arch_number = MACH_TYPE_SMDK2400;
diff --git a/board/samsung/smdk2410/smdk2410.c 
b/board/samsung/smdk2410/smdk2410.c
index 5d1a8bb..76a24bb 100644
--- a/board/samsung/smdk2410/smdk2410.c
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -73,36 +73,36 @@ int board_init (void)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     /* to reduce PLL lock time, adjust the LOCKTIME register */
-    clk_power->LOCKTIME = 0xFFFFFF;
+    clk_power->locktime = 0xFFFFFF;
 
     /* configure MPLL */
-    clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+    clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
     /* some delay between MPLL and UPLL */
     delay (4000);
 
     /* configure UPLL */
-    clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+    clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
     /* some delay between MPLL and UPLL */
     delay (8000);
 
     /* set up the I/O ports */
-    gpio->GPACON = 0x007FFFFF;
-    gpio->GPBCON = 0x00044555;
-    gpio->GPBUP = 0x000007FF;
-    gpio->GPCCON = 0xAAAAAAAA;
-    gpio->GPCUP = 0x0000FFFF;
-    gpio->GPDCON = 0xAAAAAAAA;
-    gpio->GPDUP = 0x0000FFFF;
-    gpio->GPECON = 0xAAAAAAAA;
-    gpio->GPEUP = 0x0000FFFF;
-    gpio->GPFCON = 0x000055AA;
-    gpio->GPFUP = 0x000000FF;
-    gpio->GPGCON = 0xFF95FFBA;
-    gpio->GPGUP = 0x0000FFFF;
-    gpio->GPHCON = 0x002AFAAA;
-    gpio->GPHUP = 0x000007FF;
+    gpio->gpacon = 0x007FFFFF;
+    gpio->gpbcon = 0x00044555;
+    gpio->gpbup = 0x000007FF;
+    gpio->gpccon = 0xAAAAAAAA;
+    gpio->gpcup = 0x0000FFFF;
+    gpio->gpdcon = 0xAAAAAAAA;
+    gpio->gpdup = 0x0000FFFF;
+    gpio->gpecon = 0xAAAAAAAA;
+    gpio->gpeup = 0x0000FFFF;
+    gpio->gpfcon = 0x000055AA;
+    gpio->gpfup = 0x000000FF;
+    gpio->gpgcon = 0xFF95FFBA;
+    gpio->gpgup = 0x0000FFFF;
+    gpio->gphcon = 0x002AFAAA;
+    gpio->gphup = 0x000007FF;
 
     /* arch number of SMDK2410-Board */
     gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c
index 3a93677..19b732c 100644
--- a/board/sbc2410x/sbc2410x.c
+++ b/board/sbc2410x/sbc2410x.c
@@ -80,40 +80,40 @@ int board_init (void)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     /* to reduce PLL lock time, adjust the LOCKTIME register */
-    clk_power->LOCKTIME = 0xFFFFFF;
+    clk_power->locktime = 0xFFFFFF;
 
     /* configure MPLL */
-    clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+    clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
     /* some delay between MPLL and UPLL */
     delay (4000);
 
     /* configure UPLL */
-    clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+    clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
     /* some delay between MPLL and UPLL */
     delay (8000);
 
     /* set up the I/O ports */
-    gpio->GPACON = 0x007FFFFF;
-    gpio->GPBCON = 0x00044556;
-    gpio->GPBUP = 0x000007FF;
-    gpio->GPCCON = 0xAAAAAAAA;
-    gpio->GPCUP = 0x0000FFFF;
-    gpio->GPDCON = 0xAAAAAAAA;
-    gpio->GPDUP = 0x0000FFFF;
-    gpio->GPECON = 0xAAAAAAAA;
-    gpio->GPEUP = 0x0000FFFF;
-    gpio->GPFCON = 0x000055AA;
-    gpio->GPFUP = 0x000000FF;
-    gpio->GPGCON = 0xFF95FF3A;
-    gpio->GPGUP = 0x0000FFFF;
-    gpio->GPHCON = 0x0016FAAA;
-    gpio->GPHUP = 0x000007FF;
-
-    gpio->EXTINT0=0x22222222;
-    gpio->EXTINT1=0x22222222;
-    gpio->EXTINT2=0x22222222;
+    gpio->gpacon = 0x007FFFFF;
+    gpio->gpbcon = 0x00044556;
+    gpio->gpbup = 0x000007FF;
+    gpio->gpccon = 0xAAAAAAAA;
+    gpio->gpcup = 0x0000FFFF;
+    gpio->gpdcon = 0xAAAAAAAA;
+    gpio->gpdup = 0x0000FFFF;
+    gpio->gpecon = 0xAAAAAAAA;
+    gpio->gpeup = 0x0000FFFF;
+    gpio->gpfcon = 0x000055AA;
+    gpio->gpfup = 0x000000FF;
+    gpio->gpgcon = 0xFF95FF3A;
+    gpio->gpgup = 0x0000FFFF;
+    gpio->gphcon = 0x0016FAAA;
+    gpio->gphup = 0x000007FF;
+
+    gpio->extint0=0x22222222;
+    gpio->extint1=0x22222222;
+    gpio->extint2=0x22222222;
 
     /* arch number of SMDK2410-Board */
     gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c
index ca4415c..dec3c61 100644
--- a/board/trab/cmd_trab.c
+++ b/board/trab/cmd_trab.c
@@ -637,28 +637,28 @@ static int adc_read (unsigned int channel)
 
     adc_init ();
 
-    padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
-    padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
-    padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+    padc->adccon &= ~ADC_STDBM; /* select normal mode */
+    padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+    padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
 
     while (j--) {
-        if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+        if ((padc->adccon & ADC_ENABLE_START) == 0)
             break;
         udelay (1);
     }
 
     if (j == 0) {
         printf("%s: ADC timeout\n", __FUNCTION__);
-        padc->ADCCON |= ADC_STDBM; /* select standby mode */
+        padc->adccon |= ADC_STDBM; /* select standby mode */
         return -1;
     }
 
-    result = padc->ADCDAT & 0x3FF;
+    result = padc->adcdat & 0x3FF;
 
-    padc->ADCCON |= ADC_STDBM; /* select standby mode */
+    padc->adccon |= ADC_STDBM; /* select standby mode */
 
     debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
-           (padc->ADCCON >> 3) & 0x7, result);
+           (padc->adccon >> 3) & 0x7, result);
 
     /*
      * Wait for ADC to be ready for next conversion. This delay value was
@@ -676,8 +676,8 @@ static void adc_init (void)
 
     padc = s3c2400_get_base_adc();
 
-    padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
-    padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+    padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+    padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
 
     /*
      * Wait some time to avoid problem with very first call of
@@ -699,10 +699,10 @@ static void led_set (unsigned int state)
 
     switch (state) {
     case 0: /* turn LED off */
-        gpio->PADAT |= (1 << 12);
+        gpio->padat |= (1 << 12);
         break;
     case 1: /* turn LED on */
-        gpio->PADAT &= ~(1 << 12);
+        gpio->padat &= ~(1 << 12);
         break;
     default:
         break;
@@ -729,8 +729,8 @@ static void led_init (void)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     /* configure GPA12 as output and set to High -> LED off */
-    gpio->PACON &= ~(1 << 12);
-    gpio->PADAT |= (1 << 12);
+    gpio->pacon &= ~(1 << 12);
+    gpio->padat |= (1 << 12);
 }
 
 
diff --git a/board/trab/rs485.c b/board/trab/rs485.c
index 6a3a4cd..d6337d0 100644
--- a/board/trab/rs485.c
+++ b/board/trab/rs485.c
@@ -51,16 +51,16 @@ static void rs485_setbrg (void)
     reg = (33000000 / (16 * 38400)) - 1;
 
     /* FIFO enable, Tx/Rx FIFO clear */
-    uart->UFCON = 0x07;
-    uart->UMCON = 0x0;
+    uart->ufcon = 0x07;
+    uart->umcon = 0x0;
     /* Normal,No parity,1 stop,8 bit */
-    uart->ULCON = 0x3;
+    uart->ulcon = 0x3;
     /*
      * tx=level,rx=edge,disable timeout int.,enable rx error int.,
      * normal,interrupt or polling
      */
-    uart->UCON = 0x245;
-    uart->UBRDIV = reg;
+    uart->ucon = 0x245;
+    uart->ubrdiv = reg;
 
     for (i = 0; i < 100; i++);
 }
@@ -69,16 +69,16 @@ static void rs485_cfgio (void)
 {
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-    gpio->PFCON &= ~(0x3 << 2);
-    gpio->PFCON |=  (0x2 << 2); /* configure GPF1 as RXD1 */
+    gpio->pfcon &= ~(0x3 << 2);
+    gpio->pfcon |=  (0x2 << 2); /* configure GPF1 as RXD1 */
 
-    gpio->PFCON &= ~(0x3 << 6);
-    gpio->PFCON |=  (0x2 << 6); /* configure GPF3 as TXD1 */
+    gpio->pfcon &= ~(0x3 << 6);
+    gpio->pfcon |=  (0x2 << 6); /* configure GPF3 as TXD1 */
 
-    gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
-    gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */
+    gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */
+    gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */
 
-    gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
+    gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
 }
 
 /*
@@ -104,9 +104,9 @@ int rs485_getc (void)
     struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
 
     /* wait for character to arrive */
-    while (!(uart->UTRSTAT & 0x1));
+    while (!(uart->utrstat & 0x1));
 
-    return uart->URXH & 0xff;
+    return uart->urxh & 0xff;
 }
 
 /*
@@ -117,9 +117,9 @@ void rs485_putc (const char c)
     struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
 
     /* wait for room in the tx FIFO */
-    while (!(uart->UTRSTAT & 0x2));
+    while (!(uart->utrstat & 0x2));
 
-    uart->UTXH = c;
+    uart->utxh = c;
 
     /* If \n, also do \r */
     if (c == '\n')
@@ -133,7 +133,7 @@ int rs485_tstc (void)
 {
     struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
 
-    return uart->UTRSTAT & 0x1;
+    return uart->utrstat & 0x1;
 }
 
 void rs485_puts (const char *s)
@@ -172,9 +172,9 @@ static void set_rs485de(unsigned char rs485de_state)
 
     /* This is on PORT A bit 11 */
     if(rs485de_state)
-        gpio->PADAT |= (1 << 11);
+        gpio->padat |= (1 << 11);
     else
-        gpio->PADAT &= ~(1 << 11);
+        gpio->padat &= ~(1 << 11);
 }
 
 
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 828facd..f12d861 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -77,36 +77,36 @@ int board_init ()
 #ifdef CONFIG_TRAB_50MHZ
     /* change the clock to be 50 MHz 1:1:1 */
     /* MDIV:0x5c PDIV:4 SDIV:2 */
-    clk_power->MPLLCON = 0x5c042;
-    clk_power->CLKDIVN = 0;
+    clk_power->mpllcon = 0x5c042;
+    clk_power->clkdivn = 0;
 #else
     /* change the clock to be 133 MHz 1:2:4 */
     /* MDIV:0x7d PDIV:4 SDIV:1 */
-    clk_power->MPLLCON = 0x7d041;
-    clk_power->CLKDIVN = 3;
+    clk_power->mpllcon = 0x7d041;
+    clk_power->clkdivn = 3;
 #endif
 
     /* set up the I/O ports */
-    gpio->PACON = 0x3ffff;
-    gpio->PBCON = 0xaaaaaaaa;
-    gpio->PBUP  = 0xffff;
+    gpio->pacon = 0x3ffff;
+    gpio->pbcon = 0xaaaaaaaa;
+    gpio->pbup  = 0xffff;
     /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0]    */
     /*  00,    10,      10,      10,      10,      10,      10    */
-    gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+    gpio->pfcon = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
 #ifdef CONFIG_HWFLOW
     /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
-    gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
+    gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
 #else
     /* do not pull up RXD0, RXD1, TXD0, TXD1 */
-    gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+    gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
 #endif
-    gpio->PGCON = 0x0;
-    gpio->PGUP  = 0x0;
-    gpio->OPENCR= 0x0;
+    gpio->pgcon = 0x0;
+    gpio->pgup  = 0x0;
+    gpio->opencr= 0x0;
 
     /* suppress flicker of the VFDs */
-    gpio->MISCCR = 0x40;
-    gpio->PFCON |= (2<<12);
+    gpio->misccr = 0x40;
+    gpio->pfcon |= (2<<12);
 
     gd->bd->bi_arch_number = MACH_TYPE_TRAB;
 
@@ -114,8 +114,8 @@ int board_init ()
     gd->bd->bi_boot_params = 0x0c000100;
 
     /* Make sure both buzzers are turned off */
-    gpio->PDCON |= 0x5400;
-    gpio->PDDAT &= ~0xE0;
+    gpio->pdcon |= 0x5400;
+    gpio->pddat &= ~0xE0;
 
 #ifdef CONFIG_VFD
     vfd_init_clocks();
@@ -132,7 +132,7 @@ int board_init ()
 
 #ifdef CONFIG_DRIVER_S3C24X0_I2C
     /* Configure I/O ports PG5 und PG6 for I2C */
-    gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+    gpio->pgcon = (gpio->pgcon & 0x003c00) | 0x003c00;
 #endif /* CONFIG_DRIVER_S3C24X0_I2C */
 
     return 0;
@@ -341,14 +341,14 @@ static inline void SET_CS_TOUCH(void)
 {
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-    gpio->PDDAT &= 0x5FF;
+    gpio->pddat &= 0x5FF;
 }
 
 static inline void CLR_CS_TOUCH(void)
 {
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-    gpio->PDDAT |= 0x200;
+    gpio->pddat |= 0x200;
 }
 
 static void spi_init(void)
@@ -358,20 +358,20 @@ static void spi_init(void)
     int i;
 
     /* Configure I/O ports. */
-    gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
-    gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
-    gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
-    gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+    gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+    gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+    gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+    gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
 
     CLR_CS_TOUCH();
 
-    spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */
-    spi->ch[0].SPPIN = 0x01;  /* SPI-MOSI holds Level after last bit */
-    spi->ch[0].SPCON = 0x1A;  /* Polling, Prescaler, Master, CPOL=0, 
CPHA=1 */
+    spi->ch[0].sppre = 0x1F; /* Baudrate ca. 514kHz */
+    spi->ch[0].sppin = 0x01;  /* SPI-MOSI holds Level after last bit */
+    spi->ch[0].spcon = 0x1A;  /* Polling, Prescaler, Master, CPOL=0, 
CPHA=1 */
 
     /* Dummy byte ensures clock to be low. */
     for (i = 0; i < 10; i++) {
-        spi->ch[0].SPTDAT = 0xFF;
+        spi->ch[0].sptdat = 0xFF;
     }
     wait_transmit_done();
 }
@@ -380,7 +380,7 @@ static void wait_transmit_done(void)
 {
     struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
 
-    while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+    while (!(spi->ch[0].spsta & 0x01)); /* wait until transfer is done */
 }
 
 static void tsc2000_write(unsigned int page, unsigned int reg,
@@ -394,13 +394,13 @@ static void tsc2000_write(unsigned int page, 
unsigned int reg,
     command |= (page << 11);
     command |= (reg << 5);
 
-    spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+    spi->ch[0].sptdat = (command & 0xFF00) >> 8;
     wait_transmit_done();
-    spi->ch[0].SPTDAT = (command & 0x00FF);
+    spi->ch[0].sptdat = (command & 0x00FF);
     wait_transmit_done();
-    spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+    spi->ch[0].sptdat = (data & 0xFF00) >> 8;
     wait_transmit_done();
-    spi->ch[0].SPTDAT = (data & 0x00FF);
+    spi->ch[0].sptdat = (data & 0x00FF);
     wait_transmit_done();
 
     CLR_CS_TOUCH();
diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c
index 268162e..e89be31 100644
--- a/board/trab/trab_fkt.c
+++ b/board/trab/trab_fkt.c
@@ -411,28 +411,28 @@ static int adc_read (unsigned int channel)
     padc = s3c2400_get_base_adc();
     channel &= 0x7;
 
-    padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
-    padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
-    padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+    padc->adccon &= ~ADC_STDBM; /* select normal mode */
+    padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+    padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
 
     while (j--) {
-        if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+        if ((padc->adccon & ADC_ENABLE_START) == 0)
             break;
         udelay (1);
     }
 
     if (j == 0) {
         printf("%s: ADC timeout\n", __FUNCTION__);
-        padc->ADCCON |= ADC_STDBM; /* select standby mode */
+        padc->adccon |= ADC_STDBM; /* select standby mode */
         return -1;
     }
 
-    result = padc->ADCDAT & 0x3FF;
+    result = padc->adcdat & 0x3FF;
 
-    padc->ADCCON |= ADC_STDBM; /* select standby mode */
+    padc->adccon |= ADC_STDBM; /* select standby mode */
 
     debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
-           (padc->ADCCON >> 3) & 0x7, result);
+           (padc->adccon >> 3) & 0x7, result);
 
     /*
      * Wait for ADC to be ready for next conversion. This delay value was
@@ -450,8 +450,8 @@ static void adc_init (void)
 
     padc = s3c2400_get_base_adc();
 
-    padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
-    padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+    padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+    padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
 
     /*
      * Wait some time to avoid problem with very first call of
@@ -493,10 +493,10 @@ int do_power_switch (void)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     /* configure GPE7 as input */
-    gpio->PECON &= ~(0x3 << (2 * 7));
+    gpio->pecon &= ~(0x3 << (2 * 7));
 
     /* signal GPE7 from power switch is low active: 0=on , 1=off */
-    result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1;
+    result = ((gpio->pedat & (1 << 7)) == (1 << 7)) ? 0 : 1;
 
     print_identifier ();
     printf("%d\n", result);
@@ -561,17 +561,17 @@ int do_vfd_id (void)
 
     /* try to red vfd board id from the value defined by pull-ups */
 
-    pcup_old = gpio->PCUP;
-    pccon_old = gpio->PCCON;
+    pcup_old = gpio->pcup;
+    pccon_old = gpio->pccon;
 
-    gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate  GPC0...GPC3 
pull-ups */
-    gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as
+    gpio->pcup = (gpio->pcup & 0xFFF0); /* activate  GPC0...GPC3 
pull-ups */
+    gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* configure GPC0...GPC3 as
                            * inputs */
     udelay (10);            /* allow signals to settle */
-    vfd_board_id = (~gpio->PCDAT) & 0x000F;    /* read GPC0...GPC3 port 
pins */
+    vfd_board_id = (~gpio->pcdat) & 0x000F;    /* read GPC0...GPC3 port 
pins */
 
-    gpio->PCCON = pccon_old;
-    gpio->PCUP = pcup_old;
+    gpio->pccon = pccon_old;
+    gpio->pcup = pcup_old;
 
     /* print vfd_board_id to console */
     print_identifier ();
@@ -593,40 +593,40 @@ int do_buzzer (char * const *argv)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     /* set prescaler for timer 2, 3 and 4 */
-    timers->TCFG0 &= ~0xFF00;
-    timers->TCFG0 |=  0x0F00;
+    timers->tcfg0 &= ~0xFF00;
+    timers->tcfg0 |=  0x0F00;
 
     /* set divider for timer 2 */
-    timers->TCFG1 &= ~0xF00;
-    timers->TCFG1 |=  0x300;
+    timers->tcfg1 &= ~0xF00;
+    timers->tcfg1 |=  0x300;
 
     /* set frequency */
     counter = (PCLK / BUZZER_FREQ) >> 9;
-    timers->ch[2].TCNTB = counter;
-    timers->ch[2].TCMPB = counter / 2;
+    timers->ch[2].tcntb = counter;
+    timers->ch[2].tcmpb = counter / 2;
 
     if (strcmp (argv[2], "on") == 0) {
         debug ("%s: frequency: %d\n", __FUNCTION__,
                BUZZER_FREQ);
 
         /* configure pin GPD7 as TOUT2 */
-        gpio->PDCON &= ~0xC000;
-        gpio->PDCON |= 0x8000;
+        gpio->pdcon &= ~0xC000;
+        gpio->pdcon |= 0x8000;
 
         /* start */
-        timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) &
+        timers->tcon = (timers->tcon | UPDATE2 | RELOAD2) &
                 ~INVERT2;
-        timers->TCON = (timers->TCON | START2) & ~UPDATE2;
+        timers->tcon = (timers->tcon | START2) & ~UPDATE2;
         return (0);
     }
     else if (strcmp (argv[2], "off") == 0) {
         /* stop */
-        timers->TCON &= ~(START2 | RELOAD2);
+        timers->tcon &= ~(START2 | RELOAD2);
 
         /* configure GPD7 as output and set to low */
-        gpio->PDCON &= ~0xC000;
-        gpio->PDCON |= 0x4000;
-        gpio->PDDAT &= ~0x80;
+        gpio->pdcon &= ~0xC000;
+        gpio->pdcon |= 0x4000;
+        gpio->pddat &= ~0x80;
         return (0);
     }
 
@@ -640,12 +640,12 @@ int do_led (char * const *argv)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     /* configure PC14 and PC15 as output */
-    gpio->PCCON &= ~(0xF << 28);
-    gpio->PCCON |= (0x5 << 28);
+    gpio->pccon &= ~(0xF << 28);
+    gpio->pccon |= (0x5 << 28);
 
     /* configure PD0 and PD4 as output */
-    gpio->PDCON &= ~((0x3 << 8) | 0x3);
-    gpio->PDCON |= ((0x1 << 8) | 0x1);
+    gpio->pdcon &= ~((0x3 << 8) | 0x3);
+    gpio->pdcon |= ((0x1 << 8) | 0x1);
 
     switch (simple_strtoul(argv[2], NULL, 10)) {
 
@@ -655,30 +655,30 @@ int do_led (char * const *argv)
 
     case 2:
         if (strcmp (argv[3], "on") == 0)
-            gpio->PCDAT |= (1 << 14);
+            gpio->pcdat |= (1 << 14);
         else
-            gpio->PCDAT &= ~(1 << 14);
+            gpio->pcdat &= ~(1 << 14);
         return 0;
 
     case 3:
         if (strcmp (argv[3], "on") == 0)
-            gpio->PCDAT |= (1 << 15);
+            gpio->pcdat |= (1 << 15);
         else
-            gpio->PCDAT &= ~(1 << 15);
+            gpio->pcdat &= ~(1 << 15);
         return 0;
 
     case 4:
         if (strcmp (argv[3], "on") == 0)
-            gpio->PDDAT |= (1 << 0);
+            gpio->pddat |= (1 << 0);
         else
-            gpio->PDDAT &= ~(1 << 0);
+            gpio->pddat &= ~(1 << 0);
         return 0;
 
     case 5:
         if (strcmp (argv[3], "on") == 0)
-            gpio->PDDAT |= (1 << 4);
+            gpio->pddat |= (1 << 4);
         else
-            gpio->PDDAT &= ~(1 << 4);
+            gpio->pddat &= ~(1 << 4);
         return 0;
 
     default:
@@ -695,22 +695,22 @@ int do_full_bridge (char * const *argv)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     /* configure PD5 and PD6 as output */
-    gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2));
-    gpio->PDCON |= ((0x1 << 5*2) | (0x1 << 6*2));
+    gpio->pdcon &= ~((0x3 << 5*2) | (0x3 << 6*2));
+    gpio->pdcon |= ((0x1 << 5*2) | (0x1 << 6*2));
 
     if (strcmp (argv[2], "+") == 0) {
-          gpio->PDDAT |= (1 << 5);
-          gpio->PDDAT |= (1 << 6);
+          gpio->pddat |= (1 << 5);
+          gpio->pddat |= (1 << 6);
           return 0;
     }
     else if (strcmp (argv[2], "-") == 0) {
-        gpio->PDDAT &= ~(1 << 5);
-        gpio->PDDAT |= (1 << 6);
+        gpio->pddat &= ~(1 << 5);
+        gpio->pddat |= (1 << 6);
         return 0;
     }
     else if (strcmp (argv[2], "off") == 0) {
-        gpio->PDDAT &= ~(1 << 5);
-        gpio->PDDAT &= ~(1 << 6);
+        gpio->pddat &= ~(1 << 5);
+        gpio->pddat &= ~(1 << 6);
         return 0;
     }
     printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
@@ -804,15 +804,15 @@ int do_motor (char * const *argv)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     /* Configure I/O port */
-    gpio->PGCON &= ~(0x3 << 0);
-    gpio->PGCON |= (0x1 << 0);
+    gpio->pgcon &= ~(0x3 << 0);
+    gpio->pgcon |= (0x1 << 0);
 
     if (strcmp (argv[2], "on") == 0) {
-        gpio->PGDAT &= ~(1 << 0);
+        gpio->pgdat &= ~(1 << 0);
         return 0;
     }
     if (strcmp (argv[2], "off") == 0) {
-        gpio->PGDAT |= (1 << 0);
+        gpio->pgdat |= (1 << 0);
         return 0;
     }
     printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
@@ -832,36 +832,36 @@ int do_pwm (char * const *argv)
 
     if (strcmp (argv[2], "on") == 0) {
         /* configure pin GPD8 as TOUT3 */
-        gpio->PDCON &= ~(0x3 << 8*2);
-        gpio->PDCON |= (0x2 << 8*2);
+        gpio->pdcon &= ~(0x3 << 8*2);
+        gpio->pdcon |= (0x2 << 8*2);
 
         /* set prescaler for timer 2, 3 and 4 */
-        timers->TCFG0 &= ~0xFF00;
-        timers->TCFG0 |= 0x0F00;
+        timers->tcfg0 &= ~0xFF00;
+        timers->tcfg0 |= 0x0F00;
 
         /* set divider for timer 3 */
-        timers->TCFG1 &= ~(0xf << 12);
-        timers->TCFG1 |= (0x3 << 12);
+        timers->tcfg1 &= ~(0xf << 12);
+        timers->tcfg1 |= (0x3 << 12);
 
         /* set frequency */
         counter = (PCLK / PWM_FREQ) >> 9;
-        timers->ch[3].TCNTB = counter;
-        timers->ch[3].TCMPB = counter / 2;
+        timers->ch[3].tcntb = counter;
+        timers->ch[3].tcmpb = counter / 2;
 
         /* start timer */
-        timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
-        timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+        timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+        timers->tcon = (timers->tcon | START3) & ~UPDATE3;
         return 0;
     }
     if (strcmp (argv[2], "off") == 0) {
 
         /* stop timer */
-        timers->TCON &= ~(START2 | RELOAD2);
+        timers->tcon &= ~(START2 | RELOAD2);
 
         /* configure pin GPD8 as output and set to 0 */
-        gpio->PDCON &= ~(0x3 << 8*2);
-        gpio->PDCON |= (0x1 << 8*2);
-        gpio->PDDAT &= ~(1 << 8);
+        gpio->pdcon &= ~(0x3 << 8*2);
+        gpio->pdcon |= (0x1 << 8*2);
+        gpio->pddat &= ~(1 << 8);
         return 0;
     }
     printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c
index 5890624..52a1bc9 100644
--- a/board/trab/tsc2000.c
+++ b/board/trab/tsc2000.c
@@ -50,21 +50,21 @@ void tsc2000_spi_init(void)
     int i;
 
     /* Configure I/O ports. */
-    gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
-    gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
-    gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
-    gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+    gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+    gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+    gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+    gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
 
     CLR_CS_TOUCH();
 
-    spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
-    spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
-    spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
+    spi->ch[0].sppre = 0x1F; /* Baud-rate ca. 514kHz */
+    spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */
+    spi->ch[0].spcon = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
                     CPHA=1 */
 
     /* Dummy byte ensures clock to be low. */
     for (i = 0; i < 10; i++) {
-        spi->ch[0].SPTDAT = 0xFF;
+        spi->ch[0].sptdat = 0xFF;
     }
     spi_wait_transmit_done();
 }
@@ -74,7 +74,7 @@ void spi_wait_transmit_done(void)
 {
     struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
 
-    while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+    while (!(spi->ch[0].spsta & 0x01)); /* wait until transfer is done */
 }
 
 
@@ -85,13 +85,13 @@ void tsc2000_write(unsigned short reg, unsigned 
short data)
 
     SET_CS_TOUCH();
     command = reg;
-    spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+    spi->ch[0].sptdat = (command & 0xFF00) >> 8;
     spi_wait_transmit_done();
-    spi->ch[0].SPTDAT = (command & 0x00FF);
+    spi->ch[0].sptdat = (command & 0x00FF);
     spi_wait_transmit_done();
-    spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+    spi->ch[0].sptdat = (data & 0xFF00) >> 8;
     spi_wait_transmit_done();
-    spi->ch[0].SPTDAT = (data & 0x00FF);
+    spi->ch[0].sptdat = (data & 0x00FF);
     spi_wait_transmit_done();
 
     CLR_CS_TOUCH();
@@ -106,19 +106,19 @@ unsigned short tsc2000_read (unsigned short reg)
     SET_CS_TOUCH();
     command = 0x8000 | reg;
 
-    spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+    spi->ch[0].sptdat = (command & 0xFF00) >> 8;
     spi_wait_transmit_done();
-    spi->ch[0].SPTDAT = (command & 0x00FF);
+    spi->ch[0].sptdat = (command & 0x00FF);
     spi_wait_transmit_done();
 
-    spi->ch[0].SPTDAT = 0xFF;
+    spi->ch[0].sptdat = 0xFF;
     spi_wait_transmit_done();
-    data = spi->ch[0].SPRDAT;
-    spi->ch[0].SPTDAT = 0xFF;
+    data = spi->ch[0].sprdat;
+    spi->ch[0].sptdat = 0xFF;
     spi_wait_transmit_done();
 
     CLR_CS_TOUCH();
-    return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8);
+    return (spi->ch[0].sprdat & 0x0FF) | (data << 8);
 }
 
 
diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h
index 0b6253f..b67869e 100644
--- a/board/trab/tsc2000.h
+++ b/board/trab/tsc2000.h
@@ -29,45 +29,45 @@
 #define _TSC2000_H_
 
 /* temperature channel multiplexer definitions */
-#define CON_MUX0        (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 
0x00000100)
-#define CLR_MUX0        (gpio->PCDAT &= 0x0FFEF)
-#define SET_MUX0        (gpio->PCDAT |= 0x00010)
+#define CON_MUX0        (gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 
0x00000100)
+#define CLR_MUX0        (gpio->pcdat &= 0x0FFEF)
+#define SET_MUX0        (gpio->pcdat |= 0x00010)
 
-#define CON_MUX1        (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 
0x00000400)
-#define CLR_MUX1        (gpio->PCDAT &= 0x0FFDF)
-#define SET_MUX1        (gpio->PCDAT |= 0x00020)
+#define CON_MUX1        (gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 
0x00000400)
+#define CLR_MUX1        (gpio->pcdat &= 0x0FFDF)
+#define SET_MUX1        (gpio->pcdat |= 0x00020)
 
-#define CON_MUX1_ENABLE        (gpio->PCCON = (gpio->PCCON & 
0x0FFFFCFFF) | 0x00001000)
-#define CLR_MUX1_ENABLE        (gpio->PCDAT |= 0x00040)
-#define SET_MUX1_ENABLE        (gpio->PCDAT &= 0x0FFBF)
+#define CON_MUX1_ENABLE        (gpio->pccon = (gpio->pccon & 
0x0FFFFCFFF) | 0x00001000)
+#define CLR_MUX1_ENABLE        (gpio->pcdat |= 0x00040)
+#define SET_MUX1_ENABLE        (gpio->pcdat &= 0x0FFBF)
 
-#define CON_MUX2_ENABLE        (gpio->PCCON = (gpio->PCCON & 
0x0FFFF3FFF) | 0x00004000)
-#define CLR_MUX2_ENABLE        (gpio->PCDAT |= 0x00080)
-#define SET_MUX2_ENABLE        (gpio->PCDAT &= 0x0FF7F)
+#define CON_MUX2_ENABLE        (gpio->pccon = (gpio->pccon & 
0x0FFFF3FFF) | 0x00004000)
+#define CLR_MUX2_ENABLE        (gpio->pcdat |= 0x00080)
+#define SET_MUX2_ENABLE        (gpio->pcdat &= 0x0FF7F)
 
-#define CON_MUX3_ENABLE        (gpio->PCCON = (gpio->PCCON & 
0x0FFFCFFFF) | 0x00010000)
-#define CLR_MUX3_ENABLE        (gpio->PCDAT |= 0x00100)
-#define SET_MUX3_ENABLE        (gpio->PCDAT &= 0x0FEFF)
+#define CON_MUX3_ENABLE        (gpio->pccon = (gpio->pccon & 
0x0FFFCFFFF) | 0x00010000)
+#define CLR_MUX3_ENABLE        (gpio->pcdat |= 0x00100)
+#define SET_MUX3_ENABLE        (gpio->pcdat &= 0x0FEFF)
 
-#define CON_MUX4_ENABLE        (gpio->PCCON = (gpio->PCCON & 
0x0FFF3FFFF) | 0x00040000)
-#define CLR_MUX4_ENABLE        (gpio->PCDAT |= 0x00200)
-#define SET_MUX4_ENABLE        (gpio->PCDAT &= 0x0FDFF)
+#define CON_MUX4_ENABLE        (gpio->pccon = (gpio->pccon & 
0x0FFF3FFFF) | 0x00040000)
+#define CLR_MUX4_ENABLE        (gpio->pcdat |= 0x00200)
+#define SET_MUX4_ENABLE        (gpio->pcdat &= 0x0FDFF)
 
-#define CON_SEL_TEMP_V_0    (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) 
| 0x00100000)
-#define CLR_SEL_TEMP_V_0    (gpio->PCDAT &= 0x0FBFF)
-#define SET_SEL_TEMP_V_0    (gpio->PCDAT |= 0x00400)
+#define CON_SEL_TEMP_V_0    (gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) 
| 0x00100000)
+#define CLR_SEL_TEMP_V_0    (gpio->pcdat &= 0x0FBFF)
+#define SET_SEL_TEMP_V_0    (gpio->pcdat |= 0x00400)
 
-#define CON_SEL_TEMP_V_1    (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) 
| 0x00400000)
-#define CLR_SEL_TEMP_V_1    (gpio->PCDAT &= 0x0F7FF)
-#define SET_SEL_TEMP_V_1    (gpio->PCDAT |= 0x00800)
+#define CON_SEL_TEMP_V_1    (gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) 
| 0x00400000)
+#define CLR_SEL_TEMP_V_1    (gpio->pcdat &= 0x0F7FF)
+#define SET_SEL_TEMP_V_1    (gpio->pcdat |= 0x00800)
 
-#define CON_SEL_TEMP_V_2    (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) 
| 0x01000000)
-#define CLR_SEL_TEMP_V_2    (gpio->PCDAT &= 0x0EFFF)
-#define SET_SEL_TEMP_V_2    (gpio->PCDAT |= 0x01000)
+#define CON_SEL_TEMP_V_2    (gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) 
| 0x01000000)
+#define CLR_SEL_TEMP_V_2    (gpio->pcdat &= 0x0EFFF)
+#define SET_SEL_TEMP_V_2    (gpio->pcdat |= 0x01000)
 
-#define CON_SEL_TEMP_V_3    (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) 
| 0x04000000)
-#define CLR_SEL_TEMP_V_3    (gpio->PCDAT &= 0x0DFFF)
-#define SET_SEL_TEMP_V_3    (gpio->PCDAT |= 0x02000)
+#define CON_SEL_TEMP_V_3    (gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) 
| 0x04000000)
+#define CLR_SEL_TEMP_V_3    (gpio->pcdat &= 0x0DFFF)
+#define SET_SEL_TEMP_V_3    (gpio->pcdat |= 0x02000)
 
 /* TSC2000 register definition */
 #define TSC2000_REG_X        ((0 << 11) | (0 << 5))
@@ -130,7 +130,7 @@ static inline void SET_CS_TOUCH(void)
 {
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-    gpio->PDDAT &= 0x5FF;
+    gpio->pddat &= 0x5FF;
 }
 
 
@@ -138,7 +138,7 @@ static inline void CLR_CS_TOUCH(void)
 {
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-    gpio->PDDAT |= 0x200;
+    gpio->pddat |= 0x200;
 }
 
 #endif    /* _TSC2000_H_ */
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index b7eb8cc..b4b40ff 100644
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -365,12 +365,12 @@ int vfd_init_clocks (void)
     /* try to determine display type from the value
      * defined by pull-ups
      */
-    gpio->PCUP = (gpio->PCUP & 0xFFF0);    /* activate  GPC0...GPC3 
pullups */
-    gpio->PCCON = (gpio->PCCON & 0xFFFFFF00);    /* configure 
GPC0...GPC3 as inputs */
+    gpio->pcup = (gpio->pcup & 0xFFF0);    /* activate  GPC0...GPC3 
pullups */
+    gpio->pccon = (gpio->pccon & 0xFFFFFF00);    /* configure 
GPC0...GPC3 as inputs */
     /* allow signals to settle */
     for (i=0; i<10000; i++)    /* udelay isn't working yet at this 
point! */
         __asm__("NOP");
-    vfd_board_id = (~gpio->PCDAT) & 0x000F;    /* read GPC0...GPC3 port 
pins */
+    vfd_board_id = (~gpio->pcdat) & 0x000F;    /* read GPC0...GPC3 port 
pins */
 
     VFD_DISABLE;                /* activate blank for the vfd */
 
@@ -381,39 +381,39 @@ int vfd_init_clocks (void)
         /* If new board revision, then use PWM 3 as cpld-clock */
         /* Enable 500 Hz timer for fill level sensor to operate properly */
         /* Configure TOUT3 as functional pin, disable pull-up */
-        gpio->PDCON &= ~0x30000;
-        gpio->PDCON |= 0x20000;
-        gpio->PDUP |= (1 << 8);
+        gpio->pdcon &= ~0x30000;
+        gpio->pdcon |= 0x20000;
+        gpio->pdup |= (1 << 8);
 
         /* Configure the prescaler */
-        timers->TCFG0 &= ~0xff00;
-        timers->TCFG0 |= 0x0f00;
+        timers->tcfg0 &= ~0xff00;
+        timers->tcfg0 |= 0x0f00;
 
         /* Select MUX input (divider) for timer3 (1/16) */
-        timers->TCFG1 &= ~0xf000;
-        timers->TCFG1 |= 0x3000;
+        timers->tcfg1 &= ~0xf000;
+        timers->tcfg1 |= 0x3000;
 
         /* Enable autoreload and set the counter and compare
          * registers to values for the 500 Hz clock
          * (for a given  prescaler (15) and divider (16)):
          * counter = (66000000 / 500) >> 9;
          */
-        timers->ch[3].TCNTB = 0x101;
-        timers->ch[3].TCMPB = 0x101 / 2;
+        timers->ch[3].tcntb = 0x101;
+        timers->ch[3].tcmpb = 0x101 / 2;
 
         /* Start timer */
-        timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
-        timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+        timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+        timers->tcon = (timers->tcon | START3) & ~UPDATE3;
     }
 #endif
     /* If old board revision, then use vm-signal as cpld-clock */
-    lcd->LCDCON2 = 0x00FFC000;
-    lcd->LCDCON3 = 0x0007FF00;
-    lcd->LCDCON4 = 0x00000000;
-    lcd->LCDCON5 = 0x00000400;
-    lcd->LCDCON1 = 0x00000B75;
+    lcd->lcdcon2 = 0x00FFC000;
+    lcd->lcdcon3 = 0x0007FF00;
+    lcd->lcdcon4 = 0x00000000;
+    lcd->lcdcon5 = 0x00000400;
+    lcd->lcdcon1 = 0x00000B75;
     /* VM (GPD1) is used as clock for the CPLD */
-    gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008;
+    gpio->pdcon = (gpio->pdcon & 0xFFFFFFF3) | 0x00000008;
 
     return 0;
 }
@@ -485,40 +485,40 @@ int drv_vfd_init(void)
      * see manual S3C2400
      */
     /* Stopp LCD-Controller */
-    lcd->LCDCON1 = 0x00000000;
+    lcd->lcdcon1 = 0x00000000;
     /* frame buffer startadr */
-    lcd->LCDSADDR1 = gd->fb_base >> 1;
+    lcd->lcdsaddr1 = gd->fb_base >> 1;
     /* frame buffer endadr */
-    lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
-    lcd->LCDSADDR3 = ((256/4));
-    lcd->LCDCON2 = 0x000DC000;
+    lcd->lcdsaddr2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
+    lcd->lcdsaddr3 = ((256/4));
+    lcd->lcdcon2 = 0x000DC000;
     if(gd->vfd_type == VFD_TYPE_MN11236)
-        lcd->LCDCON2 = 37 << 14;    /* MN11236: 38 lines */
+        lcd->lcdcon2 = 37 << 14;    /* MN11236: 38 lines */
     else
-        lcd->LCDCON2 = 55 << 14;    /* T119C:   56 lines */
-    lcd->LCDCON3 = 0x0051000A;
-    lcd->LCDCON4 = 0x00000001;
+        lcd->lcdcon2 = 55 << 14;    /* T119C:   56 lines */
+    lcd->lcdcon3 = 0x0051000A;
+    lcd->lcdcon4 = 0x00000001;
     if (gd->vfd_type && vfd_inv_data)
-        lcd->LCDCON5 = 0x000004C0;
+        lcd->lcdcon5 = 0x000004C0;
     else
-        lcd->LCDCON5 = 0x00000440;
+        lcd->lcdcon5 = 0x00000440;
 
     /* Port pins as LCD output */
-    gpio->PCCON =   (gpio->PCCON & 0xFFFFFF00)| 0x000000AA;
-    gpio->PDCON =   (gpio->PDCON & 0xFFFFFF03)| 0x000000A8;
+    gpio->pccon =   (gpio->pccon & 0xFFFFFF00)| 0x000000AA;
+    gpio->pdcon =   (gpio->pdcon & 0xFFFFFF03)| 0x000000A8;
 
     /* Synchronize VFD enable with LCD controller to avoid flicker    */
-    lcd->LCDCON1 = 0x00000B75;            /* Start LCD-Controller    */
-    while((lcd->LCDCON5 & 0x180000)!=0x100000);    /* Wait for end of 
VSYNC */
-    while((lcd->LCDCON5 & 0x060000)!=0x040000);    /* Wait for next 
HSYNC    */
-    while((lcd->LCDCON5 & 0x060000)==0x040000);
-    while((lcd->LCDCON5 & 0x060000)!=0x000000);
+    lcd->lcdcon1 = 0x00000B75;            /* Start LCD-Controller    */
+    while((lcd->lcdcon5 & 0x180000)!=0x100000);    /* Wait for end of 
VSYNC */
+    while((lcd->lcdcon5 & 0x060000)!=0x040000);    /* Wait for next 
HSYNC    */
+    while((lcd->lcdcon5 & 0x060000)==0x040000);
+    while((lcd->lcdcon5 & 0x060000)!=0x000000);
     if(gd->vfd_type)
         VFD_ENABLE;
 
-    debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1);
-    debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2);
-    debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3);
+    debug ("LCDSADDR1: %lX\n", lcd->lcdsaddr1);
+    debug ("LCDSADDR2: %lX\n", lcd->lcdsaddr2);
+    debug ("LCDSADDR3: %lX\n", lcd->lcdsaddr3);
 
     return 0;
 }
@@ -532,8 +532,8 @@ void disable_vfd (void)
     struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
     VFD_DISABLE;
-    gpio->PDCON &= ~0xC;
-    gpio->PDUP  &= ~0x2;
+    gpio->pdcon &= ~0xC;
+    gpio->pdup  &= ~0x2;
 }
 
 /************************************************************************/
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index c8371cf..ba6f39b 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -58,10 +58,10 @@ static int GetI2CSDA(void)
     struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 
 #ifdef CONFIG_S3C2410
-    return (readl(&gpio->GPEDAT) & 0x8000) >> 15;
+    return (readl(&gpio->gpedat) & 0x8000) >> 15;
 #endif
 #ifdef CONFIG_S3C2400
-    return (readl(&gpio->PGDAT) & 0x0020) >> 5;
+    return (readl(&gpio->pgdat) & 0x0020) >> 5;
 #endif
 }
 
@@ -77,10 +77,10 @@ static void SetI2CSCL(int x)
     struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 
 #ifdef CONFIG_S3C2410
-    writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, 
&gpio->GPEDAT);
+    writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, 
&gpio->gpedat);
 #endif
 #ifdef CONFIG_S3C2400
-    writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT);
+    writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
 #endif
 }
 
@@ -90,26 +90,26 @@ static int WaitForXfer(void)
     int i;
 
     i = I2C_TIMEOUT * 10000;
-    while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) {
+    while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
         udelay(100);
         i--;
     }
 
-    return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
+    return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
 }
 
 static int IsACK(void)
 {
     struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
 
-    return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK);
+    return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
 }
 
 static void ReadWriteByte(void)
 {
     struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
 
-    writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON);
+    writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 }
 
 void i2c_init(int speed, int slaveadd)
@@ -122,30 +122,30 @@ void i2c_init(int speed, int slaveadd)
     /* wait for some time to give previous transfer a chance to finish */
 
     i = I2C_TIMEOUT * 1000;
-    while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) {
+    while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) {
         udelay(1000);
         i--;
     }
 
-    if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
+    if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
 #ifdef CONFIG_S3C2410
-        ulong old_gpecon = readl(&gpio->GPECON);
+        ulong old_gpecon = readl(&gpio->gpecon);
 #endif
 #ifdef CONFIG_S3C2400
-        ulong old_gpecon = readl(&gpio->PGCON);
+        ulong old_gpecon = readl(&gpio->pgcon);
 #endif
         /* bus still busy probably by (most) previously interrupted
            transfer */
 
 #ifdef CONFIG_S3C2410
         /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
-        writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000,
-               &gpio->GPECON);
+        writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
+               &gpio->gpecon);
 #endif
 #ifdef CONFIG_S3C2400
         /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
-        writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000,
-               &gpio->PGCON);
+        writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
+               &gpio->pgcon);
 #endif
 
         /* toggle I2CSCL until bus idle */
@@ -164,10 +164,10 @@ void i2c_init(int speed, int slaveadd)
 
         /* restore pin functions */
 #ifdef CONFIG_S3C2410
-        writel(old_gpecon, &gpio->GPECON);
+        writel(old_gpecon, &gpio->gpecon);
 #endif
 #ifdef CONFIG_S3C2400
-        writel(old_gpecon, &gpio->PGCON);
+        writel(old_gpecon, &gpio->pgcon);
 #endif
     }
 
@@ -183,13 +183,13 @@ void i2c_init(int speed, int slaveadd)
 
     /* set prescaler, divisor according to freq, also set
      * ACKGEN, IRQ */
-    writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON);
+    writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
 
     /* init to SLAVE REVEIVE and set slaveaddr */
-    writel(0, &i2c->IICSTAT);
-    writel(slaveadd, &i2c->IICADD);
+    writel(0, &i2c->iicstat);
+    writel(slaveadd, &i2c->iicadd);
     /* program Master Transmit (and implicit STOP) */
-    writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
+    writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 
 }
 
@@ -218,47 +218,47 @@ int i2c_transfer(unsigned char cmd_type,
 
     /* Check I2C bus idle */
     i = I2C_TIMEOUT * 1000;
-    while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) {
+    while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
         udelay(1000);
         i--;
     }
 
-    if (readl(&i2c->IICSTAT) & I2CSTAT_BSY)
+    if (readl(&i2c->iicstat) & I2CSTAT_BSY)
         return I2C_NOK_TOUT;
 
-    writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON);
+    writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon);
     result = I2C_OK;
 
     switch (cmd_type) {
     case I2C_WRITE:
         if (addr && addr_len) {
-            writel(chip, &i2c->IICDS);
+            writel(chip, &i2c->iicds);
             /* send START */
             writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
-                   &i2c->IICSTAT);
+                   &i2c->iicstat);
             i = 0;
             while ((i < addr_len) && (result == I2C_OK)) {
                 result = WaitForXfer();
-                writel(addr[i], &i2c->IICDS);
+                writel(addr[i], &i2c->iicds);
                 ReadWriteByte();
                 i++;
             }
             i = 0;
             while ((i < data_len) && (result == I2C_OK)) {
                 result = WaitForXfer();
-                writel(data[i], &i2c->IICDS);
+                writel(data[i], &i2c->iicds);
                 ReadWriteByte();
                 i++;
             }
         } else {
-            writel(chip, &i2c->IICDS);
+            writel(chip, &i2c->iicds);
             /* send START */
             writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
-                   &i2c->IICSTAT);
+                   &i2c->iicstat);
             i = 0;
             while ((i < data_len) && (result = I2C_OK)) {
                 result = WaitForXfer();
-                writel(data[i], &i2c->IICDS);
+                writel(data[i], &i2c->iicds);
                 ReadWriteByte();
                 i++;
             }
@@ -268,42 +268,42 @@ int i2c_transfer(unsigned char cmd_type,
             result = WaitForXfer();
 
         /* send STOP */
-        writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
+        writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
         ReadWriteByte();
         break;
 
     case I2C_READ:
         if (addr && addr_len) {
-            writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
-            writel(chip, &i2c->IICDS);
+            writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
+            writel(chip, &i2c->iicds);
             /* send START */
-            writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
-                   &i2c->IICSTAT);
+            writel(readl(&i2c->iicstat) | I2C_START_STOP,
+                   &i2c->iicstat);
             result = WaitForXfer();
             if (IsACK()) {
                 i = 0;
                 while ((i < addr_len) && (result == I2C_OK)) {
-                    writel(addr[i], &i2c->IICDS);
+                    writel(addr[i], &i2c->iicds);
                     ReadWriteByte();
                     result = WaitForXfer();
                     i++;
                 }
 
-                writel(chip, &i2c->IICDS);
+                writel(chip, &i2c->iicds);
                 /* resend START */
                 writel(I2C_MODE_MR | I2C_TXRX_ENA |
-                       I2C_START_STOP, &i2c->IICSTAT);
+                       I2C_START_STOP, &i2c->iicstat);
                 ReadWriteByte();
                 result = WaitForXfer();
                 i = 0;
                 while ((i < data_len) && (result == I2C_OK)) {
                     /* disable ACK for final READ */
                     if (i == data_len - 1)
-                        writel(readl(&i2c->IICCON)
-                               & ~0x80, &i2c->IICCON);
+                        writel(readl(&i2c->iiccon)
+                               & ~0x80, &i2c->iiccon);
                     ReadWriteByte();
                     result = WaitForXfer();
-                    data[i] = readl(&i2c->IICDS);
+                    data[i] = readl(&i2c->iicds);
                     i++;
                 }
             } else {
@@ -311,11 +311,11 @@ int i2c_transfer(unsigned char cmd_type,
             }
 
         } else {
-            writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
-            writel(chip, &i2c->IICDS);
+            writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
+            writel(chip, &i2c->iicds);
             /* send START */
-            writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
-                   &i2c->IICSTAT);
+            writel(readl(&i2c->iicstat) | I2C_START_STOP,
+                   &i2c->iicstat);
             result = WaitForXfer();
 
             if (IsACK()) {
@@ -323,11 +323,11 @@ int i2c_transfer(unsigned char cmd_type,
                 while ((i < data_len) && (result == I2C_OK)) {
                     /* disable ACK for final READ */
                     if (i == data_len - 1)
-                        writel(readl(&i2c->IICCON) &
-                               ~0x80, &i2c->IICCON);
+                        writel(readl(&i2c->iiccon) &
+                               ~0x80, &i2c->iiccon);
                     ReadWriteByte();
                     result = WaitForXfer();
-                    data[i] = readl(&i2c->IICDS);
+                    data[i] = readl(&i2c->iicds);
                     i++;
                 }
             } else {
@@ -336,7 +336,7 @@ int i2c_transfer(unsigned char cmd_type,
         }
 
         /* send STOP */
-        writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
+        writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
         ReadWriteByte();
         break;
 
diff --git a/drivers/mtd/nand/s3c2410_nand.c 
b/drivers/mtd/nand/s3c2410_nand.c
index a27d47e..821c9fc 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -84,7 +84,7 @@ static int s3c2410_dev_ready(struct mtd_info *mtd)
 {
     struct s3c2410_nand *nand = s3c2410_get_base_nand();
     debugX(1, "dev_ready\n");
-    return readl(&nand->NFSTAT) & 0x01;
+    return readl(&nand->nfstat) & 0x01;
 }
 
 #ifdef CONFIG_S3C2410_NAND_HWECC
@@ -92,7 +92,7 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, 
int mode)
 {
     struct s3c2410_nand *nand = s3c2410_get_base_nand();
     debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
-    writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF);
+    writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
 }
 
 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const 
u_char *dat,
@@ -130,7 +130,7 @@ int board_nand_init(struct nand_chip *nand)
 
     debugX(1, "board_nand_init()\n");
 
-    writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+    writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 
     /* initialize hardware */
     twrph0 = 3;
@@ -144,7 +144,7 @@ int board_nand_init(struct nand_chip *nand)
     writel(cfg, &nand_reg->NFCONF);
 
     /* initialize nand_chip data structure */
-    nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
+    nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
 
     nand->select_chip = NULL;
 
diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c
index 04de5ca..7f02f05 100644
--- a/drivers/rtc/s3c24x0_rtc.c
+++ b/drivers/rtc/s3c24x0_rtc.c
@@ -49,11 +49,11 @@ static inline void SetRTC_Access(RTC_ACCESS a)
 
     switch (a) {
     case RTC_ENABLE:
-        writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON);
+        writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon);
         break;
 
     case RTC_DISABLE:
-        writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON);
+        writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon);
         break;
     }
 }
@@ -71,23 +71,23 @@ int rtc_get(struct rtc_time *tmp)
 
     /* read RTC registers */
     do {
-        sec  = readb(&rtc->BCDSEC);
-        min  = readb(&rtc->BCDMIN);
-        hour = readb(&rtc->BCDHOUR);
-        mday = readb(&rtc->BCDDATE);
-        wday = readb(&rtc->BCDDAY);
-        mon  = readb(&rtc->BCDMON);
-        year = readb(&rtc->BCDYEAR);
-    } while (sec != readb(&rtc->BCDSEC));
+        sec  = readb(&rtc->bcdsec);
+        min  = readb(&rtc->bcdmin);
+        hour = readb(&rtc->bcdhour);
+        mday = readb(&rtc->bcddate);
+        wday = readb(&rtc->bcdday);
+        mon  = readb(&rtc->bcdmon);
+        year = readb(&rtc->bcdyear);
+    } while (sec != readb(&rtc->bcdsec));
 
     /* read ALARM registers */
-    a_sec   = readb(&rtc->ALMSEC);
-    a_min   = readb(&rtc->ALMMIN);
-    a_hour  = readb(&rtc->ALMHOUR);
-    a_date  = readb(&rtc->ALMDATE);
-    a_mon   = readb(&rtc->ALMMON);
-    a_year  = readb(&rtc->ALMYEAR);
-    a_armed = readb(&rtc->RTCALM);
+    a_sec   = readb(&rtc->almsec);
+    a_min   = readb(&rtc->almmin);
+    a_hour  = readb(&rtc->almhour);
+    a_date  = readb(&rtc->almdate);
+    a_mon   = readb(&rtc->almmon);
+    a_year  = readb(&rtc->almyear);
+    a_armed = readb(&rtc->rtcalm);
 
     /* disable access to RTC registers */
     SetRTC_Access(RTC_DISABLE);
@@ -145,13 +145,13 @@ int rtc_set(struct rtc_time *tmp)
     SetRTC_Access(RTC_ENABLE);
 
     /* write RTC registers */
-    writeb(sec, &rtc->BCDSEC);
-    writeb(min, &rtc->BCDMIN);
-    writeb(hour, &rtc->BCDHOUR);
-    writeb(mday, &rtc->BCDDATE);
-    writeb(wday, &rtc->BCDDAY);
-    writeb(mon, &rtc->BCDMON);
-    writeb(year, &rtc->BCDYEAR);
+    writeb(sec, &rtc->bcdsec);
+    writeb(min, &rtc->bcdmin);
+    writeb(hour, &rtc->bcdhour);
+    writeb(mday, &rtc->bcddate);
+    writeb(wday, &rtc->bcdday);
+    writeb(mon, &rtc->bcdmon);
+    writeb(year, &rtc->bcdyear);
 
     /* disable access to RTC registers */
     SetRTC_Access(RTC_DISABLE);
@@ -163,8 +163,8 @@ void rtc_reset(void)
 {
     struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
 
-    writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON);
-    writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON);
+    writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon);
+    writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon);
 }
 
 #endif
diff --git a/drivers/serial/serial_s3c24x0.c 
b/drivers/serial/serial_s3c24x0.c
index 8a3e302..f42b15e 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -101,7 +101,7 @@ void _serial_setbrg(const int dev_index)
     /* value is calculated so : (int)(PCLK/16./baudrate) -1 */
     reg = get_PCLK() / (16 * gd->baudrate) - 1;
 
-    writel(reg, &uart->UBRDIV);
+    writel(reg, &uart->ubrdiv);
     for (i = 0; i < 100; i++)
         /* Delay */ ;
 }
@@ -131,26 +131,26 @@ static int serial_init_dev(const int dev_index)
 #endif
 
     /* FIFO enable, Tx/Rx FIFO clear */
-    writel(0x07, &uart->UFCON);
-    writel(0x0, &uart->UMCON);
+    writel(0x07, &uart->ufcon);
+    writel(0x0, &uart->umcon);
 
     /* Normal,No parity,1 stop,8 bit */
-    writel(0x3, &uart->ULCON);
+    writel(0x3, &uart->ulcon);
     /*
      * tx=level,rx=edge,disable timeout int.,enable rx error int.,
      * normal,interrupt or polling
      */
-    writel(0x245, &uart->UCON);
+    writel(0x245, &uart->ucon);
 
 #ifdef CONFIG_HWFLOW
-    writel(0x1, &uart->UMCON);    /* RTS up */
+    writel(0x1, &uart->umcon);    /* rts up */
 #endif
 
     /* FIXME: This is sooooooooooooooooooo ugly */
 #if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2)
     /* we need auto hw flow control on the gsm and gps port */
     if (dev_index == 0 || dev_index == 1)
-        writel(0x10, &uart->UMCON);
+        writel(0x10, &uart->umcon);
 #endif
     _serial_setbrg(dev_index);
 
@@ -176,10 +176,10 @@ int _serial_getc(const int dev_index)
 {
     struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 
-    while (!(readl(&uart->UTRSTAT) & 0x1))
+    while (!(readl(&uart->utrstat) & 0x1))
         /* wait for character to arrive */ ;
 
-    return readb(&uart->URXH) & 0xff;
+    return readb(&uart->urxh) & 0xff;
 }
 
 #if defined(CONFIG_SERIAL_MULTI)
@@ -237,15 +237,15 @@ void _serial_putc(const char c, const int dev_index)
         return;
 #endif
 
-    while (!(readl(&uart->UTRSTAT) & 0x2))
+    while (!(readl(&uart->utrstat) & 0x2))
         /* wait for room in the tx FIFO */ ;
 
 #ifdef CONFIG_HWFLOW
-    while (hwflow && !(readl(&uart->UMSTAT) & 0x1))
+    while (hwflow && !(readl(&uart->umstat) & 0x1))
         /* Wait for CTS up */ ;
 #endif
 
-    writeb(c, &uart->UTXH);
+    writeb(c, &uart->utxh);
 
     /* If \n, also do \r */
     if (c == '\n')
@@ -272,7 +272,7 @@ int _serial_tstc(const int dev_index)
 {
     struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 
-    return readl(&uart->UTRSTAT) & 0x1;
+    return readl(&uart->utrstat) & 0x1;
 }
 
 #if defined(CONFIG_SERIAL_MULTI)
-- 
1.7.1



Minkyu Kang wrote:
> Dear C Nauman,
>
> On 23 August 2010 22:40, C Nauman <cnauman at diagraph.com> wrote:
>   
>> This patch adds generic support for the Samsung s3c2440 processor.
>> Started from patch posted 2009-06-19 by
>>  Kevin Morfitt. Then modified for changes in the code that have occurred
>> since.
>>
>> Signed-off-by: Craig Nauman <cnauman <at> diagraph.com>
>>     
>
> Please fix the email address.
> And could you please use the git format-patch?
> so that we can see what are changed.
>
>   
>> ---
>>
>> diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
>> index 15f53dd..d4abd24 100644
>> --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
>> +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
>> @@ -82,6 +82,10 @@ struct s3c24x0_interrupt {
>>        u32     SUBSRCPND;
>>        u32     INTSUBMSK;
>>  #endif
>> +#ifdef CONFIG_S3C2440
>> +       u32     SUBSRCPND;
>> +       u32     INTSUBMSK;
>> +#endif
>>  };
>>     
>
> We don't allow upper case structure members.
> That is reason for why kevin sent clean-up patches.
> Please fix it globally.
>
> Thanks.
> Minkyu Kang.
>   

-- 
Craig Nauman
Diagraph an ITW Company
cnauman at diagraph dot com



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