[U-Boot] [PATCH][v4] powerpc: eSPI and eSPI controller support

[Wolfgang Denk]

Dear Shaohui Xie,

In message <1303796554-29675-1-git-send-email-b21989 at freescale.com> you wrote:
> From: Mingkai Hu <Mingkai.hu at freescale.com>
> 
> Signed-off-by: Mingkai Hu <Mingkai.hu at freescale.com>
> Singed-off-by: Jerry Huang <Chang-Ming.Huang at freescale.com>
> Signed-off-by: Shaohui Xie <b21989 at freescale.com>
> Cc: Mike Frysinger <vapier at gentoo.org>
...
> +		if (pm > 16) {
> +			pm = 16;
> +			debug("Requested speed is too low: %d Hz"
> +			" %d Hz is used.\n", max_hz, spibrg / (32 * 16));

Please indent continuation lines.

...
> +				/* Set up the next iteration if sending > 4 bytes */

Line to long.  Please fix globally.


> --- a/include/spi.h
> +++ b/include/spi.h
> @@ -2,6 +2,8 @@
>   * (C) Copyright 2001
>   * Gerald Van Baren, Custom IDEAS, vanbaren at cideas.com.
>   *
> + * Copyright 2010-2011 Freescale Semiconductor, Inc
> + *
>   * See file CREDITS for list of people who contributed to this
>   * project.
>   *
> @@ -26,13 +28,6 @@
>  
>  /* Controller-specific definitions: */
>  
> -/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
> -#ifdef CONFIG_MPC8XXX_SPI
> -# ifndef CONFIG_HARD_SPI
> -#  define CONFIG_HARD_SPI
> -# endif
> -#endif
> -
>  /* SPI mode flags */
>  #define	SPI_CPHA	0x01			/* clock phase */
>  #define	SPI_CPOL	0x02			/* clock polarity */

Please omit this part.  The deletion of 6 lines of code is not
something which earns FSL any copyright.

Best regards,

Wolfgang Denk

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