[U-Boot] p2020 and Micron MT47H64M16HR memory and u-boot

[Felix Radensky]

Hi Wojtek,

On 12/09/2011 08:20 AM, wzab <wzab01 at gmail.com> wrote:
>
> Well, it seems that the integrated DDR controller is able to perform
> the full initialization procedure with DLL reset.
> Anyway we are not able to read data written into the DDR.
>
> Could someone share the correct P2020 DDR controller settings for
> MT47H64M16HR-25E working with 667MT/s rate?
> -- 
> TIA&  Regards,
> Wojtek
>

I have P2020 based board with 512MB of MT47H64M16HR-25:H memory
running at 800MHz rate. It works fine with u-boot-2010.06.  Something
have changed in later u-boot versions, because I had no luck with 
u-boot-2011.03
on P1022 based based board with the same memory, and had to switch back to
u-boot-2010.06. Unfortunately I had no time to find out the root of 
the problem.

Below is my DDR controller configuration. I hope you'll find it useful.
Please note that I had to extend struct fsl_ddr_cfg_regs_s, defined in
arch/powerpc/include/asm/fsl_ddr_sdram.h, adding cdr1 and cdr2 registers,
so that I can control ODT values. I've also added code to 
fsl_ddr_set_memctl_regs()
routine, defined in arch/powerpc/cpu/mpc85xx/ddr-gen3.c  to configure 
these registers.


#define CONFIG_SYS_DDR_CS0_BNDS                0x0000001F
#define CONFIG_SYS_DDR_CS0_CONFIG             0x80014102
#define CONFIG_SYS_DDR_CS0_CONFIG_2         0x00000000
#define CONFIG_SYS_DDR_INIT_ADDR               0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR       0x00000000
#define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
#define CONFIG_SYS_DDR_ZQ_CONTROL           0x00000000
#define CONFIG_SYS_DDR_WRLVL_CONTROL    0x00000000
#define CONFIG_SYS_DDR_SR_CNTR                 0x00000000
#define CONFIG_SYS_DDR_RCW_1                     0x00000000
#define CONFIG_SYS_DDR_RCW_2                     0x00000000
#define CONFIG_SYS_DDR_CONTROL                 0x03000008
#define CONFIG_SYS_DDR_CONTROL_2             0x24401010
#define CONFIG_SYS_DDR_TIMING_4                0x00000000
#define CONFIG_SYS_DDR_TIMING_5                0x00000000
#define CONFIG_SYS_DDR_CDR1                      0x00000000
#define CONFIG_SYS_DDR_CDR2                      0x00000000

#define CONFIG_SYS_DDR_TIMING_3_800    0x00020000
#define CONFIG_SYS_DDR_TIMING_0_800    0x00220A02
#define CONFIG_SYS_DDR_TIMING_1_800    0x606BB643
#define CONFIG_SYS_DDR_TIMING_2_800    0x032868D2
#define CONFIG_SYS_DDR_CLK_CTRL_800   0x02000000
#define CONFIG_SYS_DDR_MODE_1_800      0x40440862
#define CONFIG_SYS_DDR_MODE_2_800      0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800    0x0A280000

fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
     .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
     .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
     .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
     .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
     .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
     .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
     .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
     .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
     .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
     .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
     .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
     .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
     .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
     .ddr_data_init = CONFIG_MEM_INIT_VALUE,
     .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
     .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
     .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
     .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
     .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
     .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
     .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
     .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
     .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
     .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2,
     .ddr_cdr1 = CONFIG_SYS_DDR_CDR1,
     .ddr_cdr2 = CONFIG_SYS_DDR_CDR2
};

Felix.