[U-Boot] [PATCH] dcache: Dcache line size aligned stack buffer allocation
Aneesh V
aneesh at ti.com
Thu Sep 1 13:13:36 CEST 2011
Hi Mike,
On Tuesday 30 August 2011 09:14 PM, Mike Frysinger wrote:
> On Thursday, August 25, 2011 05:34:00 Wolfgang Denk wrote:
>> CONFIG_SYS_CACHELINE_SIZE is a mandatory #define, and it's OK that a
>> build breaks when it's missing. On the other hand I don;t se why this
>> macro needs top be removed when the data cache is off.
>
> i guess a lot of arch people will need to post updates. this seems to be
> available for all ppc and mips peeps, and one arm soc. everyone else gets a
> fun build fail.
That's indeed a problem.
>
> however, cacheline size is an aspect of the cpu core and doesnt really make
> sense as a board config. even the ppc header hints at this:
> /*
> * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
> */
> #ifndef CONFIG_SYS_CACHELINE_SIZE
> #define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
> #endif
>
> so my proposal is to migrate away from CONFIG_SYS_CACHELINE_SIZE and to the
> API that Linux has adopted:
> asm/cache.h: define L1_CACHE_BYTES, L1_CACHE_SHIFT, and ARCH_DMA_MINALIGN
Not sure how this will work though. Cache-line is not same for ARM
architectures or even sub-architectures. For instance Cortex-A8 and
Cortex-A9(both armv7) have different cache-line sizes. So, asm/cache.h
should probably have something like:
#ifdef CONFIG_CORTEXA8
#define L1_CACHE_BYTES x
...
#elif CONFIG_CORTEXA9
...
#endif
Even this wouldn't work straight away because use of flags such as
CONFIG_CORTEXA8 is also not standard. But, that may be a better thing
to fix than adding CONFIG_SYS_CACHELINE_SIZE in all the board config
files.
Am I missing something?
best regards,
Aneesh
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