[U-Boot] [PATCH] dcache: Dcache line size aligned stack buffer allocation

[Mike Frysinger]

On Thursday, September 01, 2011 07:13:36 Aneesh V wrote:
> On Tuesday 30 August 2011 09:14 PM, Mike Frysinger wrote:
> > however, cacheline size is an aspect of the cpu core and doesnt really
> > make sense as a board config.  even the ppc header hints at this:
> > /*
> > 
> >  * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
> >  */
> > 
> > #ifndef CONFIG_SYS_CACHELINE_SIZE
> > #define CONFIG_SYS_CACHELINE_SIZE   L1_CACHE_BYTES
> > #endif
> > 
> > so my proposal is to migrate away from CONFIG_SYS_CACHELINE_SIZE and to
> > the API that Linux has adopted:
> > asm/cache.h: define L1_CACHE_BYTES, L1_CACHE_SHIFT, and ARCH_DMA_MINALIGN
> 
> Not sure how this will work though. Cache-line is not same for ARM
> architectures or even sub-architectures.

each arch is responsible for making sure the right value bubbles up.  if that 
means they have to tail into asm/arch/cache.h, that's the arch's problem.

keep in mind, this is the API already in use by Linux, so they must have 
solved the issue there for the pile of SoC's they support (and i'm fairly 
certain they support just as many as us if not more).
-mike
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