[U-Boot] U-Boot for AMCC Sequoia Board (PPC440EPX) fails to boot for version 2009.11-rc1 onwards

[Hayes,Doug]

I removed the same 2 calls from the latest U-Boot (2011.06) and it boots to U-Boot prompt as well. Not sure how to set the card to 33MHz, it may already start at 33MHz.  The documentation on SW2 doesn't mention PCI settings (our current setting for SW2 is 4321:OFF,ON,OFF,ON?).  We are using Bootstrap Option C which comes up at PCI 33 MHz then I assume is changed to 66MHz by SW?

On another note do you know if EHCI is supported for the USB host controller on the Sequioa 440EPX in the latest U-Boot. OHCI runs no problem but when I compile for EHCI it doesn't see devices when plugged in.  There is an errata [USB23] for this device which doesn't appear fixed here which may be the cause of this (but the code in U-Boot doesn't match the Linux code where the patch comes from).  Just wanted to know if EHCI is supported at all (there is some code there).  Thanks.

Doug

-----Original Message-----
From: Stefan Roese [mailto:sr at denx.de] 
Sent: Friday, September 09, 2011 10:38 AM
To: Hayes,Doug
Cc: U-Boot-Users
Subject: Re: [U-Boot] U-Boot for AMCC Sequoia Board (PPC440EPX) fails to boot for version 2009.11-rc1 onwards

Doug,

(Please keep the list on CC. Other might have comments or be interested in 
this thread).

On Friday 09 September 2011 15:54:29 Hayes,Doug wrote:
> Removed a 2nd call to ppc4xx_pci_sync_clock_config()  in checkBoard() and
> now I get to the U-Boot prompt.  Perhaps this function has a problem with
> 66MHz PCI or something about the set up of my card?  I will try removing
> those calls in the latest U-boot to see if it will run.  Let me know if
> you have any ideas about this code.  Thanks again.

This reminds me of a problem with PCI clocks on 440EP(x)/GR(x). Please take a 
look at this commit:

---
commit 5e47f9535f53fd4cc05f32fb6166870f976fbb4e
Author: Stefan Roese <sr at denx.de>
Date:   Mon Oct 19 14:06:23 2009 +0200

    ppc4xx: Add function to check and dynamically change PCI sync clock
    
    PPC440EP(x)/PPC440GR(x):
    In asynchronous PCI mode, the synchronous PCI clock must meet
    certain requirements. The following equation describes the
    relationship that must be maintained between the asynchronous PCI
    clock and synchronous PCI clock. Select an appropriate PCI:PLB
    ratio to maintain the relationship:
    
    AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
    
    This patch now adds a function to check and reconfigure the sync
    PCI clock to meet this requirement. This is in preparation for
    some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this
    function to not violate the PCI clocking rules.

    Signed-off-by: Stefan Roese <sr at denx.de>
---

This commit is included in v2009.11-rc1. So it definitely seems to point to 
the problem you are seeing on your board. I have to admit though, that I don't 
understand why this doesn't work for your Sequoia.

Could you check if the board boots fine with PCI sync clock forced to 33MHz 
(switch SW2). And please re-check if the equation from the commit text above 
is met in your case.

BTW: Why do you use a fixed strapping (non-bootstrap EEPROM)? You could alwys 
use "chip_config" to configure the EEPROM and configure the board to use the 
EEPROM strapping values.

Best regards,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
The information contained in this electronic mail transmission 
may be privileged and confidential, and therefore, protected 
from disclosure. If you have received this communication in 
error, please notify us immediately by replying to this 
message and deleting it from your computer without copying 
or disclosing it.