[U-Boot] [PATCH 3/9] powerpc/mpc8548: Add workaround for erratum NMG_DDR120

[Zhao Chenhui]

From: chenhui zhao <chenhui.zhao at freescale.com>

Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some
early version silicons. The default settings of the DDR IO receiver
biasing may not work at cold temperature. When a failure occurs,
a DDR input latches an incorrect value. The workaround will set the
receiver to an acceptable bias point.

Signed-off-by: Gong Chen <g.chen at freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao at freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    4 ++++
 arch/powerpc/cpu/mpc85xx/ddr-gen2.c       |   22 +++++++++++++++++++++-
 arch/powerpc/include/asm/config_mpc85xx.h |    1 +
 3 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 0478ec1..f0fa0f5 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -96,6 +96,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 	puts("Work-around for Erratum IFC A-003399 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+		puts("Work-around for Erratum NMG DDR120 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
index 655f99c..a71fb42 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/processor.h>
 #include <asm/fsl_ddr_sdram.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@@ -19,12 +20,31 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 {
 	unsigned int i;
 	volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint svr;
+#endif
 
 	if (ctrl_num) {
 		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 		return;
 	}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	/*
+	 * Set the DDR IO receiver to an acceptable bias point.
+	 * Fixed in Rev 2.1.
+	 */
+	svr = get_svr();
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
+		if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
+		   SDRAM_CFG_SDRAM_TYPE_DDR2)
+			out_be32(&gur->ddrioovcr, 0x90000000);
+		else
+			out_be32(&gur->ddrioovcr, 0xA8000000);
+	}
+#endif
+
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (i == 0) {
 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f9bf80d..a0a12b2 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -62,6 +62,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1
-- 
1.6.4.1