[U-Boot] [PATCH 2/2] mmc: tegra: invalidate complete cachelines

[Mike Frysinger]

On Tuesday 24 April 2012 03:53:44 Thierry Reding wrote:
> The MMC core sometimes reads buffers that are smaller than a complete
> cacheline, for example when reading the SCR. In order to avoid a warning
> from the ARM v7 cache handling code, this patch makes sure that complete
> cachelines are flushed.

this is still wrong.  all you've done is bypass the error message without 
addressing the underlying problem -- you're invalidating too much.
-mike
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