[U-Boot] [PATCH 2/2] mmc: tegra: invalidate complete cachelines

[Thierry Reding]

* Mike Frysinger wrote:
> On Tuesday 24 April 2012 03:53:44 Thierry Reding wrote:
> > The MMC core sometimes reads buffers that are smaller than a complete
> > cacheline, for example when reading the SCR. In order to avoid a warning
> > from the ARM v7 cache handling code, this patch makes sure that complete
> > cachelines are flushed.
> 
> this is still wrong.  all you've done is bypass the error message without 
> addressing the underlying problem -- you're invalidating too much.

Reading 8 bytes is always less than a cacheline, so we don't have much
choice, do we? We could of course always read a whole cacheline even if only
8 bytes are requested, but does that have any advantage over reading 8 bytes
and then invalidating the cacheline?

Or maybe I'm missing the point.

Thierry
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