[U-Boot] ROM_SI_REV on MX5

[Benoît Thébaudeau]

Hi Matt,

> >> Can anyone tell me where this offset is in relation to, or what
> >> it's
> >> actually meant to be?
> >>
> >> Some parts of U-Boot read it out but I can't figure any part of
> >> the
> >> docs that refers to this magic 0x48 offset or what it could be (or
> >> what it should be when you read it out)?
> >
> > See "Figure 9-1. Internal ROM and RAM Memory Map" in the i.MX51 RM.
> > This is the
> > only reference to it that I find in the RM. All the details
> > probably come from
> > FSL's code. I think that it's close to IIM.SREV, if not the same.
> > It's supposed
> > to be a ROM version, but it's used like a silicon/tapeout revision.
> 
> We've got several boards that seem to randomly change ROM_SI_REV
> contents on random boots (one of them went from rev2.5 to rev2.0 to
> rev3.0 and back again), and looking at the details on a TO3..
> IIM.SILICON_REV reports 0x10 for the revision of a TO3, so that's an
> identifier for that I think, otherwise it's 0x00. For silicon
> revision
> 2.0, 2.5 I can't confirm this data at location 0x48 of the memory map
> though. For TO3 the copyright string for the i.MX boot ROM has
> basically gone (it's not random data at 0x00000000 though, it's
> exactly the same every time..)

How do you read ROM_SI_REV? With the md command? With the silicon revision
printed by U-Boot on startup?

When it changes, is it always after the same reset cause (POR, WDT, etc.)?

> Looking at the GPIO registers I can't even confirm that the
> directions
> we're setting in U-Boot are correct, although U-Boot is doing what we
> consider to be "the right thing".. the board revisions come out fine
> from PCBID.

What do you mean by "can't"? What do you get if you read the GPIO DIR registers?

Best regards,
Benoît