[U-Boot] [PATCH v2 7/7] Tegra30: Add/enable Cardhu build (T30 reference board)

[Stephen Warren]

On 12/04/2012 01:40 PM, Lucas Stach wrote:
> Hi Tom,
> 
> Am Dienstag, den 04.12.2012, 13:22 -0700 schrieb Tom Warren:
> [...]
>>
>>>
>>>> +#define V_NS16550_CLK                        216000000       /* 216MHz (pllp_out0) */
>>>
>>> I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
>>> up that way.
>>
>> See my previous reply. In the internal U-Boot repo I ported from, PLLP
>> was initially set to 216MHz, then sped up to 408MHz. When this first
>> round of patches is in, I can address going to 408MHz first thing.
>>
> Is running the PLL_P at 408MHz something which requires a lot of work?
> If not, please do this and fold it into this patchset. It doesn't look
> too nice adding things to upstream which have to be changed/removed
> immediately after going in.

Naively I'd have to agree here; it seems that programming the PLL for
the correct rate would probably "just work" right from the outset? After
all, if the code runs OK with the higher rate enabled a little later in
boot, I see no reason it shouldn't run OK with that exact same rate the
whole way through.