[U-Boot] [PATCH v9 1/4] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro

[Chander Kashyap]

CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4)
architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ
to make it generic for exynos architecture.

Signed-off-by: Chander Kashyap <chander.kashyap at linaro.org>
---
Changes for v2:
	- None
Changes for v3:
	- None
Changes for V4:
	- Added CONFIG_SYS_CLK_FREQ to trats.h
Changes for v5:
	- None
Changes for v6:
	- None
Changes for v7:
	- None
Changes for v8:
	- None
Changes for v9:
	- None

 arch/arm/cpu/armv7/exynos/clock.c   |    6 +-----
 include/configs/s5pc210_universal.h |    1 +
 include/configs/trats.h             |    1 +
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 0c199cd..4d92c53 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,10 +26,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_CLK_FREQ_C210
-#define CONFIG_SYS_CLK_FREQ_C210	24000000
-#endif
-
 /* exynos4: return pll clock frequency */
 static unsigned long exynos4_get_pll_clk(int pllreg)
 {
@@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
 	/* SDIV [2:0] */
 	s = r & 0x7;
 
-	freq = CONFIG_SYS_CLK_FREQ_C210;
+	freq = CONFIG_SYS_CLK_FREQ;
 
 	if (pllreg == EPLL) {
 		k = k & 0xffff;
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index be000cb..8286680 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -49,6 +49,7 @@
 
 /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
 #define CONFIG_SYS_CLK_FREQ_C210	24000000
+#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/trats.h b/include/configs/trats.h
index acb3241..10f11d9 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -49,6 +49,7 @@
 
 /* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
 #define CONFIG_SYS_CLK_FREQ_C210	24000000
+#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
-- 
1.7.5.4