[U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Robert Deliën]

> That is because not only CPU running @ PLL, HBUS also source from P_CLK, we switch
> CPU clock to XTAL, the HBUS clock also slow down.

You're right, but I'm not switching back to XTAL. I'm just postponing the switch to PLL. Not
in the last reason because the first switch to PLL is incorrect (and shouldn't even work).