[U-Boot] [PATCH] armv7: omap3: leave outer cache enabled

[Aneesh V]

Mainline kernel for OMAP3 doesn't enable L2 cache
It expects L2$ to be enabled by ROM-code/bootloader.

Leaving L2$ enabled can be troublesome in cases where
the L2 cache is not under CP15 control, such as in
Cortex-A9. This problem is explained in detail in
the commit dc7100f4080952798413fb63bb4134b22c57623a

However, this problem doesn't apply to Cortex-A8
because L2$ in Cortex-A8 is under CP15 control and
hence the generic armv7 maintenance opertions work
for it.

As such we can make an exception for OMAP3 and
leave the L2$ enabled when we jump to kernel. This
is done by removing the strongly-linked implementation
of v7_outer_cache_disable() and allowing it to fall
back to the weakly linked implementation that doesn't
do anything.

Signed-off-by: Aneesh V <aneesh at ti.com>
---
I haven't tested this patch as I don't have an OMAP3
board with me right now. Appreciate if anybody with
a Beagle could try it out.
---
 arch/arm/cpu/armv7/omap3/board.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 871aa37..21cf455 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -426,7 +426,7 @@ void v7_outer_cache_enable(void)
 	omap3_update_aux_cr(0x2, 0);
 }
 
-void v7_outer_cache_disable(void)
+void omap3_outer_cache_disable(void)
 {
 	/* Clear L2EN */
 	omap3_update_aux_cr_secure(0, 0x2);
-- 
1.7.1