[U-Boot] [PATCH v2 2/5] armv7: add appropriate headers for assembly functions
Aneesh V
aneesh at ti.com
Thu Feb 23 14:39:42 CET 2012
Use ENTRY and ENDPROC with assembly functions to ensure
necessary assembler directives for all functions.
Signed-off-by: Aneesh V <aneesh at ti.com>
---
Changes in V2:
- Newly added
---
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 5 ++-
arch/arm/cpu/armv7/mx6/lowlevel_init.S | 5 ++-
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 14 ++++----
arch/arm/cpu/armv7/omap-common/reset.S | 5 ++-
arch/arm/cpu/armv7/omap3/lowlevel_init.S | 41 ++++++++++++-----------
arch/arm/cpu/armv7/s5pc1xx/cache.S | 10 +++--
arch/arm/cpu/armv7/s5pc1xx/reset.S | 5 ++-
arch/arm/cpu/armv7/start.S | 13 ++++---
arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 5 ++-
arch/arm/cpu/armv7/u8500/lowlevel.S | 9 +++--
10 files changed, 61 insertions(+), 51 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 01f6d75..5344410 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -22,6 +22,7 @@
#include <config.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
+#include <linux/linkage.h>
/*
* L2CC Cache setup/invalidation/disable
@@ -312,8 +313,7 @@
.section ".text.init", "x"
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
#if defined(CONFIG_MX51)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
@@ -334,6 +334,7 @@ lowlevel_init:
/* r12 saved upper lr*/
mov pc,lr
+ENDPROC(lowlevel_init)
/* Board level setting value */
W_DP_OP_864: .word DP_OP_864
diff --git a/arch/arm/cpu/armv7/mx6/lowlevel_init.S b/arch/arm/cpu/armv7/mx6/lowlevel_init.S
index 1864356..acadef2 100644
--- a/arch/arm/cpu/armv7/mx6/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx6/lowlevel_init.S
@@ -18,7 +18,8 @@
*/
.section ".text.init", "x"
-.globl lowlevel_init
-lowlevel_init:
+#include <linux/linkage.h>
+ENTRY(lowlevel_init)
mov pc, lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 35f38ac..ccc6bb6 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -27,9 +27,9 @@
*/
#include <asm/arch/omap.h>
+#include <linux/linkage.h>
-.global save_boot_params
-save_boot_params:
+ENTRY(save_boot_params)
/*
* See if the rom code passed pointer is valid:
* It is not valid if it is not in non-secure SRAM
@@ -76,10 +76,9 @@ save_boot_params:
strb r2, [r3, #CH_FLAGS_OFFSET]
1:
bx lr
+ENDPROC(save_boot_params)
-
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
/*
* Setup a temporary stack
*/
@@ -95,12 +94,13 @@ lowlevel_init:
*/
bl s_init
pop {ip, pc}
+ENDPROC(lowlevel_init)
-.globl set_pl310_ctrl_reg
-set_pl310_ctrl_reg:
+ENTRY(set_pl310_ctrl_reg)
PUSH {r4-r11, lr} @ save registers - ROM code may pollute
@ our registers
LDR r12, =0x102 @ Set PL310 control register - value in R0
.word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
@ call ROM Code API to set control register
POP {r4-r11, pc}
+ENDPROC(set_pl310_ctrl_reg)
diff --git a/arch/arm/cpu/armv7/omap-common/reset.S b/arch/arm/cpu/armv7/omap-common/reset.S
index 838b122..179a476 100644
--- a/arch/arm/cpu/armv7/omap-common/reset.S
+++ b/arch/arm/cpu/armv7/omap-common/reset.S
@@ -22,9 +22,9 @@
*/
#include <config.h>
+#include <linux/linkage.h>
-.global reset_cpu
-reset_cpu:
+ENTRY(reset_cpu)
ldr r1, rstctl @ get addr for global reset
@ reg
ldr r3, rstbit @ sw reset bit
@@ -36,3 +36,4 @@ rstctl:
.word PRM_RSTCTRL
rstbit:
.word PRM_RSTCTRL_RESET
+ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index c42c5dd..ebf69fa 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -31,22 +31,22 @@
#include <version.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks_omap3.h>
+#include <linux/linkage.h>
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
#ifdef CONFIG_SPL_BUILD
-.global save_boot_params
-save_boot_params:
+ENTRY(save_boot_params)
ldr r4, =omap3_boot_device
ldr r5, [r0, #0x4]
and r5, r5, #0xff
str r5, [r4]
bx lr
+ENDPROC(save_boot_params)
#endif
-.global omap3_gp_romcode_call
-omap3_gp_romcode_call:
+ENTRY(omap3_gp_romcode_call)
PUSH {r4-r12, lr} @ Save all registers from ROM code!
MOV r12, r0 @ Copy the Service ID in R12
MOV r0, r1 @ Copy parameter to R0
@@ -55,6 +55,7 @@ omap3_gp_romcode_call:
.word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
@ because we use -march=armv5
POP {r4-r12, pc}
+ENDPROC(omap3_gp_romcode_call)
/*
* Funtion for making PPA HAL API calls in secure devices
@@ -62,8 +63,7 @@ omap3_gp_romcode_call:
* R0 - Service ID
* R1 - paramer list
*/
-.global do_omap3_emu_romcode_call
-do_omap3_emu_romcode_call:
+ENTRY(do_omap3_emu_romcode_call)
PUSH {r4-r12, lr} @ Save all registers from ROM code!
MOV r12, r0 @ Copy the Secure Service ID in R12
MOV r3, r1 @ Copy the pointer to va_list in R3
@@ -76,14 +76,14 @@ do_omap3_emu_romcode_call:
.word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
@ because we use -march=armv5
POP {r4-r12, pc}
+ENDPROC(do_omap3_emu_romcode_call)
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
/**************************************************************************
* cpy_clk_code: relocates clock code into SRAM where its safer to execute
* R1 = SRAM destination address.
*************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
+ENTRY(cpy_clk_code)
/* Copy DPLL code into SRAM */
adr r0, go_to_speed /* get addr of clock setting code */
mov r2, #384 /* r2 size to copy (div by 32 bytes) */
@@ -95,6 +95,7 @@ next2:
cmp r0, r2 /* until source end address [r2] */
bne next2
mov pc, lr /* back to caller */
+ENDPROC(cpy_clk_code)
/* ***************************************************************************
* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
@@ -109,8 +110,7 @@ next2:
* L3 when its not in self refresh seems bad for it. Normally, this
* code runs from flash before SDR is init so that should be ok.
****************************************************************************/
-.global go_to_speed
- go_to_speed:
+ENTRY(go_to_speed)
stmfd sp!, {r4 - r6}
/* move into fast relock bypass */
@@ -171,6 +171,7 @@ wait2:
nop
ldmfd sp!, {r4 - r6}
mov pc, lr /* back to caller, locked */
+ENDPROC(go_to_speed)
_go_to_speed: .word go_to_speed
@@ -211,8 +212,7 @@ pll_div_val5:
#endif
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
@@ -230,6 +230,7 @@ lowlevel_init:
/* back to arch calling code */
mov pc, lr
+ENDPROC(lowlevel_init)
/* the literal pools origin */
.ltorg
@@ -480,22 +481,22 @@ per_36x_dpll_param:
.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
-.globl get_36x_mpu_dpll_param
-get_36x_mpu_dpll_param:
+ENTRY(get_36x_mpu_dpll_param)
adr r0, mpu_36x_dpll_param
mov pc, lr
+ENDPROC(get_36x_mpu_dpll_param)
-.globl get_36x_iva_dpll_param
-get_36x_iva_dpll_param:
+ENTRY(get_36x_iva_dpll_param)
adr r0, iva_36x_dpll_param
mov pc, lr
+ENDPROC(get_36x_iva_dpll_param)
-.globl get_36x_core_dpll_param
-get_36x_core_dpll_param:
+ENTRY(get_36x_core_dpll_param)
adr r0, core_36x_dpll_param
mov pc, lr
+ENDPROC(get_36x_core_dpll_param)
-.globl get_36x_per_dpll_param
-get_36x_per_dpll_param:
+ENTRY(get_36x_per_dpll_param)
adr r0, per_36x_dpll_param
mov pc, lr
+ENDPROC(get_36x_per_dpll_param)
diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S
index c7d6221..000192c 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/cache.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S
@@ -25,20 +25,22 @@
.align 5
+#include <linux/linkage.h>
+
#ifndef CONFIG_SYS_L2CACHE_OFF
-.global v7_outer_cache_enable
-v7_outer_cache_enable:
+ENTRY(v7_outer_cache_enable)
push {r0, r1, r2, lr}
mrc 15, 0, r3, cr1, cr0, 1
orr r3, r3, #2
mcr 15, 0, r3, cr1, cr0, 1
pop {r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_enable)
-.global v7_outer_cache_disable
-v7_outer_cache_disable:
+ENTRY(v7_outer_cache_disable)
push {r0, r1, r2, lr}
mrc 15, 0, r3, cr1, cr0, 1
bic r3, r3, #2
mcr 15, 0, r3, cr1, cr0, 1
pop {r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_disable)
#endif
diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S
index 70fa146..c7a41d0 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/reset.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/reset.S
@@ -22,12 +22,12 @@
*/
#include <asm/arch/cpu.h>
+#include <linux/linkage.h>
#define S5PC100_SWRESET 0xE0200000
#define S5PC110_SWRESET 0xE0102000
-.globl reset_cpu
-reset_cpu:
+ENTRY(reset_cpu)
ldr r1, =S5PC100_PRO_ID
ldr r2, [r1]
ldr r4, =0x00010000
@@ -45,3 +45,4 @@ reset_cpu:
str r2, [r1]
_loop_forever:
b _loop_forever
+ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index ef08a55..261835b 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -33,6 +33,7 @@
#include <config.h>
#include <version.h>
#include <asm/system.h>
+#include <linux/linkage.h>
.globl _start
_start: b reset
@@ -172,8 +173,7 @@ call_board_init_f:
* after relocating the monitor code.
*
*/
- .globl relocate_code
-relocate_code:
+ENTRY(relocate_code)
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
@@ -289,6 +289,7 @@ jump_2_ram:
_board_init_r_ofs:
.word board_init_r - _start
+ENDPROC(relocate_code)
/*************************************************************************
*
@@ -298,8 +299,7 @@ _board_init_r_ofs:
* CONFIG_SYS_ICACHE_OFF is defined.
*
*************************************************************************/
-.globl cpu_init_cp15
-cpu_init_cp15:
+ENTRY(cpu_init_cp15)
/*
* Invalidate L1 I/D
*/
@@ -325,7 +325,7 @@ cpu_init_cp15:
#endif
mcr p15, 0, r0, c1, c0, 0
mov pc, lr @ back to my caller
-
+ENDPROC(cpu_init_cp15)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
@@ -336,7 +336,7 @@ cpu_init_cp15:
* setup memory timing
*
*************************************************************************/
-cpu_init_crit:
+ENTRY(cpu_init_crit)
/*
* Jump to board specific initialization...
* The Mask ROM will have already initialized
@@ -347,6 +347,7 @@ cpu_init_crit:
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
+ENDPROC(cpu_init_crit)
#endif
#ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
index 6b86647..d117f23 100644
--- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
@@ -25,10 +25,10 @@
#include <config.h>
#include <version.h>
+#include <linux/linkage.h>
.align 5
-.global reset_cpu
-reset_cpu:
+ENTRY(reset_cpu)
ldr r1, rstctl @ get addr for global reset
@ reg
ldr r3, [r1]
@@ -39,3 +39,4 @@ _loop_forever:
b _loop_forever
rstctl:
.word PRM_RSTCTRL
+ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/armv7/u8500/lowlevel.S b/arch/arm/cpu/armv7/u8500/lowlevel.S
index cffdfd1..289cfb0 100644
--- a/arch/arm/cpu/armv7/u8500/lowlevel.S
+++ b/arch/arm/cpu/armv7/u8500/lowlevel.S
@@ -20,16 +20,17 @@
*/
#include <config.h>
+#include <linux/linkage.h>
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
mov pc, lr
+ENDPROC(lowlevel_init)
.align 5
-.globl reset_cpu
-reset_cpu:
+ENTRY(reset_cpu)
ldr r0, =CFG_PRCMU_BASE
ldr r1, =0x1
str r1, [r0, #0x228]
_loop_forever:
b _loop_forever
+ENDPROC(reset_cpu)
--
1.7.1
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