[U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it.

[Aneesh V]

On Friday 20 January 2012 02:51 PM, Christian Riesch wrote:
> Hi Aneesh,
>
> On Fri, Jan 20, 2012 at 9:52 AM, Aneesh V<aneesh at ti.com>  wrote:
>> Sughosh,
> [...]
>> Can you send the value of SCR you found at SPL entry? This will clarify
>> what's enabled and what's not.
>
> I would like to try that on my board as well for comparison. Could you
> please tell me how this register can be read? In the ARM manuals SCR
> seems to have several meanings... Thank you!
> Regards, Christian

If you have a JTAG based debugger that has the capability of displaying
CP15 registers, look for "CP15 System Control Register". Otherwise you
will have to read it using an assembly instruction like below:

	mrc	p15, 0, r0, c1, c0, 0

After this instruction r0 will contain the SCR value. arm926ejs/start.S
has this instruction at line #367. You can put a breakpoint after this
and look at r0.

br,
Aneesh