[U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it.

[Christian Riesch]

Hi Aneesh,

On Fri, Jan 20, 2012 at 1:13 PM, Aneesh V <aneesh at ti.com> wrote:
> On Friday 20 January 2012 02:51 PM, Christian Riesch wrote:
>> On Fri, Jan 20, 2012 at 9:52 AM, Aneesh V<aneesh at ti.com>  wrote:
>>> Sughosh,
>>
>> [...]
>>>
>>> Can you send the value of SCR you found at SPL entry? This will clarify
>>> what's enabled and what's not.
>>
>> I would like to try that on my board as well for comparison. Could you
>> please tell me how this register can be read? In the ARM manuals SCR
>> seems to have several meanings... Thank you!
>> Regards, Christian
>
> If you have a JTAG based debugger that has the capability of displaying
> CP15 registers, look for "CP15 System Control Register". Otherwise you
> will have to read it using an assembly instruction like below:
>
>
>        mrc     p15, 0, r0, c1, c0, 0
>
> After this instruction r0 will contain the SCR value. arm926ejs/start.S
> has this instruction at line #367. You can put a breakpoint after this
> and look at r0.

Thank you!

I don't have a JTAG debugger so I stored it in a register, pushed it
later to the stack and then read it with md.l from the memory. I tried
it on my custom board (AM1808 SoC, direct boot from NOR flash) and on
both the da850evm (with AM1808 SoC, AIS boot from SPI flash). The
result was the same for both cases, 0x00052078. So DCache and ICache
are disabled after the RBL.
Regards, Christian