[U-Boot] [PATCH] smsc95xx: align buffers to cache line size

[Marek Vasut]

Dear Ilya Yanok,

> Dear Marek,
> 
> On Mon, Jul 9, 2012 at 1:31 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > > non-ARMv7 system now to do some testing...
> > > But it used to work without any alignment, right? (with disabled
> > > dcache,
> > 
> > of
> > 
> > > course)
> > > That makes me think that data buffers don't need any alignment (from
> > > USB pov, not cache) and 32-byte alignment is required for internal
> > > structs only.
> > > 
> > > Hm.. I have to admit I'm not very much into USB specs and I don't have
> > 
> > any
> > See ehci-r10.pdf ... chapter 3.5 ... the buffer pointer has to be aligned
> > too it
> > seems.
> 
> But in practice it works without any alignment... ok, you made me read the
> spec ;)
> page 55: "For the page 0 current offset interpretation, this field is the
> byte offset into the current page"

See the thread
"[U-Boot] [PATCH] usb_storage: fix ehci driver max transfer size"

So, if we compute the size over there correctly (I hope Stefan will send an 
updated patch soon), we'll still need it to be aligned to ARCH_DMA_MINALIGN so 
we can flush it. Bah, this is getting quite crazy, the deeper we go, the more 
bugs we meet!

So, what I'd like to do is to see a patch from Stefan, it was really a good 
finding! Next up, we should finish this patchset for proper EHCI QH and qTD 
alignment. And finally, we need generic bounce buffer to use as a protection 
against crazy people who might want to load stuff to unaligned address.

> Regards, Ilya.

Best regards,
Marek Vasut