[U-Boot] [PATCH] smsc95xx: align buffers to cache line size

[Ilya Yanok]

Dear Marek,

On Mon, Jul 9, 2012 at 4:45 AM, Marek Vasut <marek.vasut at gmail.com> wrote:

>
> > But in practice it works without any alignment... ok, you made me read
> the
> > spec ;)
> > page 55: "For the page 0 current offset interpretation, this field is the
> > byte offset into the current page"
>
>
> See the thread
> "[U-Boot] [PATCH] usb_storage: fix ehci driver max transfer size"
>

Interesting... but that's a different issue...


> So, if we compute the size over there correctly (I hope Stefan will send an
> updated patch soon), we'll still need it to be aligned to
> ARCH_DMA_MINALIGN so
> we can flush it. Bah, this is getting quite crazy, the deeper we go, the
> more
> bugs we meet!
>

Well, of course we need proper alignment for cache stuff (well, actually we
can skip this alignment thing for the buffer we will flush as long as all
buffers we are going to invalidate are properly aligned/sized... but that's
too tricky, personally I'd prefer every DMAed buffer to be cache-line
aligned/sized).

And this patch actually adds the alignment for the smsc95xx driver's
buffers. In your initial reply you said it will be broken on systems with
ARCH_DMA_MINALIGN < 32, so I'm asking what makes you think so?


> So, what I'd like to do is to see a patch from Stefan, it was really a good
> finding! Next up, we should finish this patchset for proper EHCI QH and qTD
> alignment. And finally, we need generic bounce buffer to use as a
> protection
> against crazy people who might want to load stuff to unaligned address.
>

Good plan.

Regards, Ilya.