[U-Boot] [PATCH 2/2] kirkwood: Add support for the D-Link DNS-320
Prafulla Wadaskar
prafulla at marvell.com
Tue Jul 31 07:56:24 CEST 2012
> -----Original Message-----
> From: Jamie Lentin [mailto:jm at lentin.co.uk]
> Sent: 31 July 2012 03:26
> To: u-boot at lists.denx.de
> Cc: Prafulla Wadaskar; albert.u.boot at aribaud.net;
> uboot at lukaperkov.net; Jamie Lentin
> Subject: [PATCH 2/2] kirkwood: Add support for the D-Link DNS-320
>
> Extend dnskw to support the D-Link DNS-320 ShareCenter NAS also. For
> more
> information on this NAS, see:-
>
> http://jamie.lentin.co.uk/devices/dlink-dns320
> http://dns323.kood.org/dns-320
> http://sharecenter.dlink.com/products/DNS-320
>
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> Cc: prafulla at marvell.com
> Cc: albert.u.boot at aribaud.net
> ---
> MAINTAINERS | 4 +
> board/d-link/dnskw/dnskw.c | 8 +-
> board/d-link/dnskw/dnskw.h | 6 +
> board/d-link/dnskw/kwbimage.dns320.cfg | 207
> ++++++++++++++++++++++++++++++++
> boards.cfg | 1 +
> include/configs/dnskw.h | 10 ++
> 6 files changed, 232 insertions(+), 4 deletions(-)
> create mode 100644 board/d-link/dnskw/kwbimage.dns320.cfg
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fd0c65c..92ede1f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -673,6 +673,10 @@ Igor Grinberg <grinberg at compulab.co.il>
>
> cm-t35 ARM ARMV7 (OMAP3xx Soc)
>
> +Jamie Lentin <jm at lentin.co.uk>
> +
> + dns320 ARM926EJS (Kirkwood SoC)
> +
> Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
>
> dns325 ARM926EJS (Kirkwood SoC)
> diff --git a/board/d-link/dnskw/dnskw.c b/board/d-link/dnskw/dnskw.c
> index d29735c..cd6bfe9 100644
> --- a/board/d-link/dnskw/dnskw.c
> +++ b/board/d-link/dnskw/dnskw.c
> @@ -58,8 +58,8 @@ int board_early_init_f(void)
> MPP10_UART0_TXD,
> MPP11_UART0_RXD,
> MPP12_SD_CLK,
> - MPP13_SD_CMD,
> - MPP14_SD_D0,
> + MPP13_UART1_TXD, /* Custom ...*/
> + MPP14_UART1_RXD, /* ... controller */
Are these entries valid for both boards? If not then encapsulate with #ifdef
> MPP15_SD_D1,
> MPP16_SD_D2,
> MPP17_SD_D3,
> @@ -74,13 +74,13 @@ int board_early_init_f(void)
> MPP26_GPIO, /* power led */
> MPP27_GPIO, /* sata0(right) error led */
> MPP28_GPIO, /* sata1(left) error led */
> - MPP29_GPIO, /* usb error led */
> + MPP29_GPIO, /* usb error led (dns-325) */
Ditto
> MPP30_GPIO,
> MPP31_GPIO,
> MPP32_GPIO,
> MPP33_GPIO,
> MPP34_GPIO, /* power key */
> - MPP35_GPIO,
> + MPP35_GPIO, /* usb error led (dns-320) */
Ditto
> MPP36_GPIO,
> MPP37_GPIO,
> MPP38_GPIO,
> diff --git a/board/d-link/dnskw/dnskw.h b/board/d-link/dnskw/dnskw.h
> index 4b11cb6..8886050 100644
> --- a/board/d-link/dnskw/dnskw.h
> +++ b/board/d-link/dnskw/dnskw.h
> @@ -43,6 +43,12 @@
> #define DNSKW_OE_VAL_HIGH 0x00000800 /* disable leds */
> #endif /* CONFIG_BOARD_IS_DNS325 */
>
> +/* DNS-320 specific configuration */
> +#ifdef CONFIG_BOARD_IS_DNS320
> +#define DNSKW_OE_VAL_LOW 0x38000000 /* disable leds */
> +#define DNSKW_OE_VAL_HIGH 0x00000808 /* disable leds */
> +#endif /* CONFIG_BOARD_IS_DNS320 */
> +
> /* PHY related */
> #define MV88E1116_MAC_CTRL_REG 21
> #define MV88E1116_PGADR_REG 22
> diff --git a/board/d-link/dnskw/kwbimage.dns320.cfg b/board/d-
> link/dnskw/kwbimage.dns320.cfg
> new file mode 100644
> index 0000000..5fb4052
> --- /dev/null
> +++ b/board/d-link/dnskw/kwbimage.dns320.cfg
> @@ -0,0 +1,207 @@
> +#
> +# Copyright (C) 2012
> +# Jamie Lentin <jm at lentin.co.uk>
> +#
> +# Based on dns325 support:
> +# Copyright (C) 2011
> +# Stefan Herbrechtsmeier <stefan at code.herbrechtsmeier.net>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> +# MA 02110-1301 USA
> +#
> +# Refer docs/README.kwimage for more details about how-to configure
> +# and create kirkwood boot image
> +#
> +
> +# Boot Media configurations
> +BOOT_FROM nand
> +NAND_ECC_MODE default
> +NAND_PAGE_SIZE 0x0800
> +
> +# SOC registers configuration using bootrom header extension
> +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> +
> +# Configure RGMII-0 interface pad voltage to 1.8V
> +DATA 0xFFD100e0 0x1b1b1b9b
> +
> +#Dram initalization for SINGLE x16 CL=3 @ 200MHz
> +DATA 0xFFD01400 0x43000618 # DDR Configuration register
> +# bit13-0: 0x618 DDR2 clks refresh rate
> +# bit23-14: 0 required
> +# bit24: 1 enable exit self refresh mode on DDR access
> +# bit25: 1 required
> +# bit29-26: 0 required
> +# bit31-30: 0b01 required
> +
> +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
> +# bit3-0: 0 required
> +# bit4: 0, addr/cmd in smame cycle
> +# bit5: 0, clk is driven during self refresh, we don't care for
> APX
> +# bit6: 0, use recommended falling edge of clk for addr/cmd
> +# bit11-7: 0 required
> +# bit12: 1 required
> +# bit13: 1 required
> +# bit14: 0, input buffer always powered up
> +# bit17-15: 0 required
> +# bit18: 1, cpu lock transaction enabled
> +# bit19: 0 required
> +# bit23-20: 1, Recommended for CL 3 and STARTBURST_DEL disabled
> +# bit27-24: 5, CL + 2
> +# bit30-28: 3 required
> +# bit31: 0, no additional STARTBURST delay
> +
> +DATA 0xFFD01408 0x11012227 # DDR Timing (Low)
> +# bit3-0: 7, 8 cycle tRAS (tRAS[3-0])
> +# bit7-4: 2, 3 cycle tRCD
> +# bit11-8: 2, 3 cycle tRP
> +# bit15-12: 2, 3 cycle tWR
> +# bit19-16: 1, 2 cycle tWTR
> +# bit20: 1, 2 cycle tRAS (tRAS[4])
> +# bit23-21: 0 required
> +# bit27-24: 1, 2 cycle tRRD
> +# bit31-28: 1, 2 cycle tRTP
> +
> +DATA 0xFFD0140C 0x00000819 # DDR Timing (High)
> +# bit6-0: 0x19, 20 cycle tRFC
> +# bit8-7: 0, 1 cycle tR2bR
> +# bit10-9: 0, 1 cycle tR2W
> +# bit12-11: 1, 1 cycle tW2W gap
> +# bit31-13: 0 required
> +
> +DATA 0xFFD01410 0x00000008 # DDR Address Control
> +# bit1-0: 0, Cs0width=x8 (out of spec?)
> +# bit3-2: 2, Cs0size=512Mb
> +# bit5-4: 0, Cs1width=nonexistent
> +# bit7-6: 0, Cs1size=nonexistent
> +# bit9-8: 0, Cs2width=nonexistent
> +# bit11-10: 0, Cs2size=nonexistent
> +# bit13-12: 0, Cs3width=nonexistent
> +# bit15-14: 0, Cs3size=nonexistent
> +# bit16: 0, Cs0AddrSel
> +# bit17: 0, Cs1AddrSel
> +# bit18: 0, Cs2AddrSel
> +# bit19: 0, Cs3AddrSel
> +# bit31-20: 0 required
> +
> +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> +# bit0: 0, OPEn=OpenPage enabled
> +# bit31-1: 0 required
> +
> +DATA 0xFFD01418 0x00000000 # DDR Operation
> +# bit3-0: 0, Cmd=Normal SDRAM Mode
> +# bit31-4: 0 required
> +
> +DATA 0xFFD0141C 0x00000632 # DDR Mode
> +# bit2-0: 2, Burst Length (2 required)
> +# bit3: 0, Burst Type (0 required)
> +# bit6-4: 3, CAS Latency (CL) 3
> +# bit7: 0, (Test Mode) Normal operation
> +# bit8: 0, (Reset DLL) Normal operation
> +# bit11-9: 3, Write recovery for auto-precharge (3 required)
> +# bit12: 0, Fast Active power down exit time (0 required)
> +# bit31-13: 0 required
> +
> +DATA 0xFFD01420 0x00000040 # DDR Extended Mode
> +# bit0: 0, DRAM DLL enabled
> +# bit1: 0, DRAM drive strength normal
> +# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
> +# bit5-3: 0 required
> +# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
> +# bit9-7: 0 required
> +# bit10: 0, differential DQS enabled
> +# bit11: 0 required
> +# bit12: 0, DRAM output buffer enabled
> +# bit31-13: 0 required
> +
> +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> +# bit2-0: 0x7 required
> +# bit3: 1, MBUS Burst Chop disabled
> +# bit6-4: 0x7 required
> +# bit7: 0 required
> +# bit8: 0, no add writepath sample stage
> +# bit9: 0, no half clock cycle addition to dataout
> +# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
> +# bit11: 0, 1/4 clock cycle skew disabled for write mesh
> +# bit15-12: 0xf required
> +# bit31-16: 0 required
> +
> +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
> +# bit3-0: 0 required
> +# bit7-4: 2, 2 cycles from read command to assertion of M_ODT
> signal
> +# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT
> signal
> +# bit15-12: 5, 5 cycles from read command to assertion of internal
> ODT signal
> +# bit19-16: 8, 8 cycles from read command to de-assertion of internal
> ODT signal
> +# bit31-20: 0 required
> +
> +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
> +# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT
> signal
> +# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT
> signal
> +# bit15-12: 5, 5 cycles from write command to assertion of internal
> ODT signal
> +# bit19-16: 8, 8 cycles from write command to de-assertion of
> internal ODT signal
> +# bit31-16: 0 required
> +
> +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
> +# bit0: 1, Window enabled
> +# bit1: 0, Write Protect disabled
> +# bit3-2: 0x0, CS0 hit selected
> +# bit23-4: 0xfffff required
> +# bit31-24: 0x07, Size (i.e. 128MB)
> +
> +DATA 0xFFD01508 0x08000000 # CS[1]n Base address to 128Mb
> +DATA 0xFFD0150C 0x0FFFFFF0 # CS[1]n Size, window disabled
> +# bit0: 0, Window disabled
> +# bit1: 0, Write Protect disabled
> +# bit3-2: 0, CS1 hit selected
> +# bit23-4: 0xfffff required
> +# bit31-24: 0x0f, Size (i.e. 256MB)
> +
> +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> +
> +DATA 0xFFD01494 0x003c0000 # DDR ODT Control (Low)
> +# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from
> DRAM
> +# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from
> DRAM
> +# bit15-8: 0 required
> +# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM
> CS2 and CS3
> +# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM
> CS0 and CS1
> +# bit31-24: 0 required
> +
> +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> +# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low
> register
> +# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low
> register
> +# bit31-4 0 required
> +
> +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
> +# bit3-0: 0b0011, internal ODT is asserted during read from DRAM
> bank 0-1
> +# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM
> bank 0-4
> +# bit9-8: 0, Internal ODT assertion is controlled by fiels
> +# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
> +# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
> +# bit14: 1, M_STARTBURST_IN ODT enabled
> +# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
> +# bit20-16: 0, Pad N channel driving strength for ODT
> +# bit25-21: 0, Pad P channel driving strength for ODT
> +# bit31-26: 0 required
> +
> +DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> +# bit0: 1, enable DDR init upon this register write
> +# bit31-1: 0, required
> +
> +# End of Header extension
> +DATA 0x0 0x0
> diff --git a/boards.cfg b/boards.cfg
> index 8b8bb45..f0de201 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -139,6 +139,7 @@ hawkboard_uart arm arm926ejs
> da8xxevm davinci
> enbw_cmc arm arm926ejs enbw_cmc
> enbw davinci
> calimain arm arm926ejs calimain
> omicron davinci
> pogo_e02 arm arm926ejs -
> cloudengines kirkwood
> +dns320 arm arm926ejs dnskw
> d-link kirkwood dnskw:BOARD_IS_DNS320
> dns325 arm arm926ejs dnskw
> d-link kirkwood dnskw:BOARD_IS_DNS325
> lschlv2 arm arm926ejs lsxl
> buffalo kirkwood lsxl:LSCHLV2
> lsxhl arm arm926ejs lsxl
> buffalo kirkwood lsxl:LSXHL
> diff --git a/include/configs/dnskw.h b/include/configs/dnskw.h
> index 2995d42..316f58a 100644
> --- a/include/configs/dnskw.h
> +++ b/include/configs/dnskw.h
> @@ -41,6 +41,16 @@
>
> #endif /* CONFIG_BOARD_IS_DNS325 */
>
> +#ifdef CONFIG_BOARD_IS_DNS320
> +#define MACH_TYPE_DNS320 3985
> +#define CONFIG_MACH_TYPE MACH_TYPE_DNS320
> +#define CONFIG_IDENT_STRING "\nD-Link DNS-320"
Can it be short? Like "DNS-320" anyways board will be D-Link.
> +
> +#define CONFIG_SYS_KWD_CONFIG
> $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.dns320.cfg
> +#define CONFIG_SYS_TCLK 166666667 /* 800Mhz */
> +
> +#endif /* CONFIG_BOARD_IS_DNS320 */
> +
> /*
> * High Level Configuration Options (easy to change)
> */
> --
Regards...
Prafulla . . .
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