[U-Boot] [PATCH 3/5] ARM: EXYNOS: add exynos lcd clock interface

[Minkyu Kang]

Donghwa,

On 30 March 2012 10:59, Donghwa Lee <dh09.lee at samsung.com> wrote:
> To get lcd source clock in EXYNOS display driver, added get_lcd_clk() interface.
>
> Signed-off-by: Donghwa Lee <dh09.lee at samsung.com>
> Signed-off-by: Inki Dae <inki.dae at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/cpu/armv7/exynos/clock.c |   50 +++++++++++++++++++++++++++++++++++++
>  1 files changed, 50 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index 2f7048b..af66d5c 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -414,6 +414,51 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
>        writel(val, addr);
>  }
>
> +/* get_lcd_clk: return lcd clock frequency */
> +static unsigned long exynos4_get_lcd_clk(void)
> +{
> +       struct exynos4_clock *clk =
> +               (struct exynos4_clock *)samsung_get_base_clock();
> +       unsigned long pclk, sclk;
> +       unsigned int sel;
> +       unsigned int ratio;
> +
> +       /*
> +        * CLK_SRC_LCD0
> +        * FIMD0_SEL [3:0]
> +        */
> +#if defined(CONFIG_EXYNOS4210)
> +       sel = readl(&clk->src_lcd0);
> +#else
> +       sel = readl(&clk->src_lcd);
> +#endif

You should split the function for exynos4 and exynos5.
Please don't use ifdef.

> +       sel = sel & 0xf;
> +
> +       if (sel == 0x6)
> +               sclk = get_pll_clk(MPLL);
> +       else if (sel == 0x7)
> +               sclk = get_pll_clk(EPLL);
> +       else if (sel == 0x8)
> +               sclk = get_pll_clk(VPLL);
> +       else
> +               return 0;
> +
> +       /*
> +        * CLK_DIV_LCD0
> +        * FIMD0_RATIO [3:0]
> +        */
> +#if defined(CONFIG_EXYNOS4210)
> +       ratio = readl(&clk->div_lcd0);
> +#else
> +       ratio = readl(&clk->div_lcd);
> +#endif
> +       ratio = ratio & 0xf;
> +
> +       pclk = sclk / (ratio + 1);
> +
> +       return pclk;
> +}
> +
>  unsigned long get_pll_clk(int pllreg)
>  {
>        if (cpu_is_exynos5())
> @@ -453,3 +498,8 @@ void set_mmc_clk(int dev_index, unsigned int div)
>        else
>                exynos4_set_mmc_clk(dev_index, div);
>  }
> +
> +unsigned long get_lcd_clk(void)
> +{
> +       return exynos4_get_lcd_clk();
> +}

Thanks.
Minkyu Kang.
-- 
from. prom.
www.promsoft.net