[U-Boot] [PATCH 4/7] OMAP5: ADD precalculated timings for ddr3

[R, Sricharan]

Hi Lokesh,

> Adding precalculated timings for ddr3 with 1cs
> adding required registers for ddr3
>
  You want to mention the part name as well ?

 nit in subject : and defining the additional registers  required
                      for  DDR3.

[snip..]

>  /* Dummy registers for OMAP44xx */
>  const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
> +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
>
>  const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
>        .dmm_lisa_map_0 = 0xFF020100,
> diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
> index b2b5753..bf7a42e 100644
> --- a/arch/arm/cpu/armv7/omap5/sdram.c
> +++ b/arch/arm/cpu/armv7/omap5/sdram.c
> @@ -86,6 +86,29 @@ const struct emif_regs emif_regs_266_mhz_2cs = {
>        .emif_ddr_ext_phy_ctrl_5        = 0x04010040
>  };
>
> +const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
> +       .sdram_config_init              = 0x61851B32,
> +       .sdram_config                   = 0x61851B32,
> +       .ref_ctrl                       = 0x00001035,
> +       .sdram_tim1                     = 0xCCCF36B3,
> +       .sdram_tim2                     = 0x308F7FDA,
> +       .sdram_tim3                     = 0x027F88A8,
> +       .read_idle_ctrl                 = 0x00050000,
> +       .zq_config                      = 0x0007190B,
> +       .temp_alert_config              = 0x00000000,
> +       .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
> +       .emif_ddr_phy_ctlr_1            = 0x0024420A,
> +       .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
> +       .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
> +       .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
> +       .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
> +       .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
> +       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
> +       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
> +       .emif_rd_wr_lvl_ctl             = 0x00000000,
> +       .emif_rd_wr_exec_thresh         = 0x00000305
> +};
> +
>  const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
>        .dmm_lisa_map_0 = 0x0,
>        .dmm_lisa_map_1 = 0,
> @@ -115,9 +138,34 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
>        0x00000077
>  };
>
> +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
> +       0x01004010,
> +       0x00001004,
> +       0x04010040,
> +       0x01004010,
> +       0x00001004,
> +       0x00000000,
> +       0x00000000,
> +       0x00000000,
> +       0x80080080,
> +       0x00800800,
> +       0x08102040,
> +       0x00000002,
> +       0x0,
> +       0x0,
> +       0x0,
> +       0x00000000,
> +       0x00000000,
> +       0x00000000,
> +       0x00000057
> +};
> +
>  static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
>  {
> -       *regs = &emif_regs_532_mhz_2cs;
> +       if (omap_revision() == OMAP5432_ES1_0)
> +               *regs = &emif_regs_ddr3_532_mhz_1cs;
> +       else
> +               *regs = &emif_regs_532_mhz_2cs;
>  }
>  void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
>        __attribute__((weak, alias("emif_get_reg_dump_sdp")));
> diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
> index f1e3ad2..5d2649e 100644
> --- a/arch/arm/include/asm/emif.h
> +++ b/arch/arm/include/asm/emif.h
> @@ -650,6 +650,7 @@ struct dmm_lisa_map_regs {
>  };
>
>  extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
> +extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
>
>  #define CS0    0
>  #define CS1    1
> @@ -1073,6 +1074,10 @@ struct emif_regs {
>        u32 emif_ddr_ext_phy_ctrl_3;
>        u32 emif_ddr_ext_phy_ctrl_4;
>        u32 emif_ddr_ext_phy_ctrl_5;
> +       u32 emif_rd_wr_lvl_rmp_win;
> +       u32 emif_rd_wr_lvl_rmp_ctl;
> +       u32 emif_rd_wr_lvl_ctl;
> +       u32 emif_rd_wr_exec_thresh;
>  };
>
>  /* assert macros */

Thanks,
 Sricharan