[U-Boot] [PATCH v3 1/2] mvgbe: allow non-sequential PHY addresses

[Albert ARIBAUD]

Signed-off-by: Albert ARIBAUD <albert.u.boot at aribaud.net>
---
Changes in v3:
- fixed building when SoC provides only one GbE port.

 arch/arm/include/asm/arch-kirkwood/kirkwood.h |    1 -
 arch/arm/include/asm/arch-orion5x/orion5x.h   |    1 -
 drivers/net/mvgbe.c                           |   12 +++++++++++-
 drivers/net/mvgbe.h                           |    7 -------
 4 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index 47771d5..503fb1e 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -61,7 +61,6 @@
 #define KW_SATA_PORT1_OFFSET		0x4000
 
 /* Kirkwood GbE controller has two ports */
-#define MAX_MVGBE_DEVS	2
 #define MVGBE0_BASE	KW_EGIGA0_BASE
 #define MVGBE1_BASE	KW_EGIGA1_BASE
 
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
index b0d3368..b32d1d3 100644
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -55,7 +55,6 @@
 #define ORION5X_SATA_PORT1_OFFSET		0x4000
 
 /* Orion5x GbE controller has a single port */
-#define MAX_MVGBE_DEVS	1
 #define MVGBE0_BASE	ORION5X_EGIGA_BASE
 
 /* Orion5x USB Host controller is port 1 */
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 47bf27c..2533614 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -49,6 +49,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define MAX_MVGBE_DEVS	2
+
 #define MV_PHY_ADR_REQUEST 0xee
 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
 
@@ -653,6 +655,14 @@ int mvgbe_initialize(bd_t *bis)
 	struct eth_device *dev;
 	int devnum;
 	u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
+#if defined(CONFIG_MVGBE_PHY_ADRS)
+#define MVGBE_PHY_ADRS CONFIG_MVGBE_PHY_ADRS
+#elif defined(CONFIG_PHY_BASE_ADR)
+#define MVGBE_PHY_ADRS {CONFIG_PHY_BASE_ADR, CONFIG_PHY_BASE_ADR+1}
+#else
+#define MVGBE_PHY_ADRS {8, 9}
+#endif
+	u8 used_phy_adrs[MAX_MVGBE_DEVS] = MVGBE_PHY_ADRS;
 
 	for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
 		/*skip if port is configured not to use */
@@ -733,7 +743,7 @@ error1:
 		miiphy_register(dev->name, smi_reg_read, smi_reg_write);
 		/* Set phy address of the port */
 		miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
-				MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
+				MV_PHY_ADR_REQUEST, used_phy_adrs[devnum]);
 #endif
 	}
 	return 0;
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index d8a5429..5434839 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -28,13 +28,6 @@
 #ifndef __MVGBE_H__
 #define __MVGBE_H__
 
-/* PHY_BASE_ADR is board specific and can be configured */
-#if defined (CONFIG_PHY_BASE_ADR)
-#define PHY_BASE_ADR		CONFIG_PHY_BASE_ADR
-#else
-#define PHY_BASE_ADR		0x08	/* default phy base addr */
-#endif
-
 /* Constants */
 #define INT_CAUSE_UNMASK_ALL		0x0007ffff
 #define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
-- 
1.7.9.5