[U-Boot] [u-boot-release] [PATCH 4/5] powerpc/85xx: Add P5040 processor support

[Kim Phillips]

On Fri, 31 Aug 2012 15:25:35 -0500
Timur Tabi <timur at freescale.com> wrote:

> Add support for the Freescale P5040 SOC, which is similar to the P5020.
> Features of the P5040 are:
> 
> Four P5040 single-threaded e5500 cores built
>     Up to 2.4 GHz with 64-bit ISA support
>     Three levels of instruction: user, supervisor, hypervisor
> CoreNet platform cache (CPC)
>     2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
> Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
>         support Up to 1600MT/s
>     Memory pre-fetch engine
> DPAA incorporating acceleration for the following functions
>     Packet parsing, classification, and distribution (FMAN)
>     Queue management for scheduling, packet sequencing and
>     congestion management (QMAN)
>     Hardware buffer management for buffer allocation and
>     de-allocation (BMAN)
>     Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes

it's a SEC 5.2, but...

>     20 lanes at up to 5 Gbps
>     Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
>     Two 10 Gbps Ethernet MACs
>     Ten 1 Gbps Ethernet MACs
> High-speed peripheral interfaces
>     Two PCI Express 2.0/3.0 controllers
> Additional peripheral interfaces
>     Two serial ATA (SATA 2.0) controllers
>     Two high-speed USB 2.0 controllers with integrated PHY
>     Enhanced secure digital host controller (SD/MMC/eMMC)
>     Enhanced serial peripheral interface (eSPI)
>     Two I2C controllers
>     Four UARTs
>     Integrated flash controller supporting NAND and NOR flash
> DMA
>     Dual four channel
> Support for hardware virtualization and partitioning enforcement
>     Extra privileged level for hypervisor support
> QorIQ Trust Architecture 1.1
>     Secure boot, secure debug, tamper detection, volatile key storage

...do we really need all this marketing text duplication anyway?
How about mentioning supported components in u-boot, as of this
patch?

> +struct liodn_id_table sec_liodn_tbl[] = {
> +	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
> +	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
> +	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
> +	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
> +	SET_SEC_RTIC_LIODN_ENTRY(a, 154),
> +	SET_SEC_RTIC_LIODN_ENTRY(b, 155),
> +	SET_SEC_RTIC_LIODN_ENTRY(c, 156),
> +	SET_SEC_RTIC_LIODN_ENTRY(d, 157),
> +	SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
> +	SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
> +};

The SEC on the P5040 has four DECOs, not two.  Plus, AFAICT, these
aren't the right values for these LIODN assignments.

Kim