[U-Boot] [PATCH V2 15/21] mx6q_4x_mt41j128.cfg: reorder for more efficient storage

[Troy Kisky]

Repeating data values can be stored more efficiently.

Signed-off-by: Troy Kisky <troy.kisky at boundarydevices.com>
---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   31 +++++++++++++-------------
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 18cdb7b..00712c6 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -60,6 +60,17 @@ IOMUX_ENTRY1(IOM_DRAM_SDQS4, 0x00000030)
 IOMUX_ENTRY1(IOM_DRAM_SDQS5, 0x00000030)
 IOMUX_ENTRY1(IOM_DRAM_SDQS6, 0x00000030)
 IOMUX_ENTRY1(IOM_DRAM_SDQS7, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B0DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B1DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B2DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B3DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B4DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B5DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B6DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_B7DS, 0x00000030)
+IOMUX_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+IOMUX_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
 
 IOMUX_ENTRY1(IOM_DRAM_DQM0, 0x00020030)
 IOMUX_ENTRY1(IOM_DRAM_DQM1, 0x00020030)
@@ -78,29 +89,17 @@ IOMUX_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
 IOMUX_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
 IOMUX_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
 IOMUX_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
-IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
 
 IOMUX_ENTRY1(IOM_DRAM_SDODT0, 0x00003030)
 IOMUX_ENTRY1(IOM_DRAM_SDODT1, 0x00003030)
 
-IOMUX_ENTRY1(IOM_GRP_B0DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B1DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B2DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B3DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B4DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B5DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B6DS, 0x00000030)
-IOMUX_ENTRY1(IOM_GRP_B7DS, 0x00000030)
-
-IOMUX_ENTRY1(IOM_GRP_ADDDS, 0x00000030)
 /* (differential input) */
 IOMUX_ENTRY1(IOM_DDRMODE_CTL, 0x00020000)
-/* disable ddr pullups */
-IOMUX_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
 /* (differential input) */
 IOMUX_ENTRY1(IOM_GRP_DDRMODE, 0x00020000)
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-IOMUX_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
+/* disable ddr pullups */
+IOMUX_ENTRY1(IOM_GRP_DDRPKE, 0x00000000)
+IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
 IOMUX_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
 
 /* Read data DQ Byte0-3 delay */
@@ -180,8 +179,8 @@ WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227)
 
 /* MPDGCTRL0/1 DQS GATE*/
 WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350)
-WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359)
 WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359)
 WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL1, 0x03650348)
 WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B)
 WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341)
-- 
1.7.9.5