[U-Boot] [PATCH] tegra30: fix UART2 pinmux table entry

[Allen Martin]

UART2_TXD and UART2_RXD mux 0 SFIO entries should be IRDA not UARTB.

Signed-off-by: Allen Martin <amartin at nvidia.com>
---
 arch/arm/cpu/tegra30-common/pinmux.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
index 122665f..8045fa1 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -149,8 +149,8 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
 	PINI(VI_MCLK,	  VI,	   VI,		VI,	   VI,      VI),
 	PINI(VI_VSYNC,	  VI,	   DDR,		RSVD2,	   VI,      RSVD4),
 	PINI(VI_HSYNC,	  VI,	   DDR,		RSVD2,	   VI,      RSVD4),
-	PINI(UART2_RXD,	  UART,	   UARTB,	SPDIF,	   UARTA,   SPI4),
-	PINI(UART2_TXD,	  UART,	   UARTB,	SPDIF,	   UARTA,   SPI4),
+	PINI(UART2_RXD,	  UART,	   IRDA,	SPDIF,	   UARTA,   SPI4),
+	PINI(UART2_TXD,	  UART,	   IRDA,	SPDIF,	   UARTA,   SPI4),
 	PINI(UART2_RTS_N, UART,	   UARTA,	UARTB,	   GMI,     SPI4),
 	PINI(UART2_CTS_N, UART,	   UARTA,	UARTB,	   GMI,     SPI4),
 	PINI(UART3_TXD,	  UART,	   UARTC,	RSVD2,	   GMI,     RSVD4),
-- 
1.7.10.4