[U-Boot] [PATCH v2 01/10] arm: move flush_dcache_all() to just before disable cache

[Albert ARIBAUD]

Hi Simon,

On Fri, 30 Nov 2012 15:01:14 -0800, Simon Glass <sjg at chromium.org>
wrote:

> From: Arun Mankuzhi <arun.m at samsung.com>
> 
> In Cortex-A15 architecture, when we run cache invalidate
> the cache clean operation executes automatically.
> So if there are any dirty cache lines before disabling the L2 cache
> these will be synchronized with the main memory when
> invalidate_dcache_all() runs in the last part of U-boot
> 
> The two functions after flush_dcache_all is using the stack. So this
> data will be on the cache. After disable when invalidate is called the
> data will be flushed from cache to memory. This corrupts the stack in
> invalida_dcache_all. So this change is required to avoid the u-boot
> hang.
> 
> So flush has to be done just before clearing CR_C bit
> 
> Signed-off-by: Arun Mankuzhi <arun.m at samsung.com>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
> Changes in v2: None
> 
>  arch/arm/lib/cache-cp15.c |    5 ++++-
>  1 files changed, 4 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index 939de10..06119c8 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -124,8 +124,11 @@ static void cache_disable(uint32_t cache_bit)
>  			return;
>  		/* if disabling data cache, disable mmu too */
>  		cache_bit |= CR_M;
> -		flush_dcache_all();
>  	}
> +	reg = get_cr();
> +	cp_delay();
> +	if (cache_bit == (CR_C | CR_M))
> +		flush_dcache_all();
>  	set_cr(reg & ~cache_bit);
>  }
>  #endif

Applied the whole series to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.