[U-Boot] [PATCH v2 7/9] tegra: add addresses of SPI SLINK controllers

[Simon Glass]

On Sat, Jan 12, 2013 at 1:07 AM, Allen Martin <amartin at nvidia.com> wrote:
> Add I/O addresses of SPI SLINK controllers 1-6
>
> Signed-off-by: Allen Martin <amartin at nvidia.com>

Acked-by: Simon Glass <sjg at chromium.org>

(optional thought below)

> ---
>  arch/arm/include/asm/arch-tegra/tegra.h |    6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
> index 67e6fd0..d2435c1 100644
> --- a/arch/arm/include/asm/arch-tegra/tegra.h
> +++ b/arch/arm/include/asm/arch-tegra/tegra.h
> @@ -40,6 +40,12 @@
>  #define NV_PA_APB_UARTE_BASE   (NV_PA_APB_MISC_BASE + 0x6400)
>  #define NV_PA_NAND_BASE                (NV_PA_APB_MISC_BASE + 0x8000)
>  #define NV_PA_SPI_BASE         (NV_PA_APB_MISC_BASE + 0xC380)
> +#define NV_PA_SLINK1_BASE      (NV_PA_APB_MISC_BASE + 0xD400)
> +#define NV_PA_SLINK2_BASE      (NV_PA_APB_MISC_BASE + 0xD600)
> +#define NV_PA_SLINK3_BASE      (NV_PA_APB_MISC_BASE + 0xD800)
> +#define NV_PA_SLINK4_BASE      (NV_PA_APB_MISC_BASE + 0xDA00)
> +#define NV_PA_SLINK5_BASE      (NV_PA_APB_MISC_BASE + 0xDC00)
> +#define NV_PA_SLINK6_BASE      (NV_PA_APB_MISC_BASE + 0xDE00)

Perhaps add #ifdef CONFIG_SPL_BUILD around this so people don't use it
accidentially?

>  #define TEGRA_DVC_BASE         (NV_PA_APB_MISC_BASE + 0xD000)
>  #define NV_PA_PMC_BASE         (NV_PA_APB_MISC_BASE + 0xE400)
>  #define NV_PA_EMC_BASE         (NV_PA_APB_MISC_BASE + 0xF400)
> --
> 1.7.10.4
>

Regards,
Simon